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CHAPTER 4 MEMORY MANAGEMENT SYSTEM
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(3) EntryLo0 (2) and EntryLo1 (3) registers
The EntryLo register consists of two registers that have identical formats: EntryLo0, used for even
virtual pages and EntryLo1, used for odd virtual pages. The EntryLo0 and EntryLo1 registers are both
read-/write-accessible. They are used to access the built-in TLB. When a TLB read/write operation is
carried out, the EntryLo0 and EntryLo1 registers hold the contents of the low-order 32 bits of TLB
entries at even and odd addresses, respectively.
Figure 4-12. EntryLo0 and EntryLo1 Registers
27
28
EntryLo1
EntryLo0
EntryLo1
EntryLo0
22
4
0
31
5
6
3
2
1
0
PFN
C
D
V
G
1
3
1
1
27
28
22
4
0
31
5
6
3
2
1
0
PFN
C
D
V
G
1
3
1
1
(a) 32-bit mode
(b) 64-bit mode
27
28
22
36
0
63
5
6
3
2
1
0
PFN
C
D
V
G
1
3
1
1
27
28
22
36
0
63
5
6
3
2
1
0
PFN
C
D
V
G
1
3
1
1
PFN:
C:
D:
Page frame number; high-order bits of the physical address.
Specifies the TLB page attribute.
Dirty. If this bit is set to 1, the page is marked as dirty and, therefore, writable. This bit is
actually a write-protect bit that software can use to prevent alteration of data.
Valid. If this bit is set to 1, it indicates that the TLB entry is valid; otherwise, a TLB Invalid
exception (TLBL or TLBS) occurs.
Global. If this bit is set in both EntryLo0 and EntryLo1, then the processor ignores the ASID
during TLB lookup.
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
V:
G:
0:
The coherency attribute (C) bits are used to specify whether to use the cache in referencing a page.
When the cache is used, whether the page attribute is “cache used” or “cache not used” is selected by
algorithm.
Table 4-6 lists the page attributes selected according to the value in the C bits.