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CHAPTER 15 PMU (POWER MANAGEMENT UNIT)
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15.1.2 Shutdown Control
A list of the states of the RTC, peripheral unit, CPU core, and the bit of PMUINTREG to be set during a
shutdown is shown below.
Table 15-2. Types of Shutdown and Processor Status
Type of shutdown
RTC
Peripheral unit
CPU core
PMUINTREG
HAL timer shutdown
Active
Reset
Cold reset
HALTIMERRST
=1
Deadman's SW shutdown
Active
Reset
Cold reset
TIMOUTRST=1
Hibernate shutdown
Active
Reset
Cold reset
-
Battery runout shutdown
Active
Reset
Cold reset
TIMOUTRST=1
Battery lock release
shutdown
Active
Reset
Cold reset
-
(1) HAL Timer Shutdown
Software is required to write 1 to the HALTMERRST bit of PMUINTREG within approx. 4 seconds after
the CPU has been restarted (the state where the shutdown state or Hibernate mode state have shifted
to the Fullspeed mode) and reset the HALTimer.
If the HAL timer is not reset within approx. 4 seconds after the CPU has been restarted, the PMU resets
all peripheral units excluding the RTC and PMU by asserting the rst
—
gab signal (internal) and resets the
CPU core by asserting the cooldresetb and creset signals (internal).
Further, it sets the TIMOUTRST bit of PMUINTREG to 1. After the CPU has been restarted, the
TIMOUTRST bit must be checked and cleared by software.
(2) Deadman's SW Shutdown
When the Deadman's SW shutdown function has been enabled, software is required to write 1 to the
DSWCLR bit of DSUCLRREG at each set time to clear the Deadman's SW counter (Refer to Chapter 17
for details).
If the Deadman's SW counter is not cleared within the set time, the PMU resets all peripheral units
excluding the RTC and PMU by asserting the rst
gab signal (internal) and resets the CPU core by
asserting the cooldresetb and creset signals (internal).
Further, it sets the DMSRST bit of PMUINTREG to 1. After the CPU has been restarted, the
TIMOUTRST bit must be checked and cleared by software.
(3) Software Shutdown
When the HIBERNATE instruction is executed, the PMU checks for the interrupts that are now on
pending. When there are no interrupts on pending, it stops the CPU clock by asserting the cclockstopen
signal. Further, it resets all peripheral units excluding the RTC and PMU by asserting the rst_gab signal
(internal).
The contents of the PMU register are left unchanged.