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CHAPTER 5 EXCEPTION PROCESSING
106
5.4.7 Address Error Exception
Cause
The Address Error exception occurs when an attempt is made to execute one of the following. This
exception is not maskable.
"
Execution of the LW, LWU, SW, or CACHE instruction for word data that is not located on a word
boundary
"
Execution of the LH, LHU, or SH instruction for half-word data that is not located on a half-word
boundary
"
Execution the LD or SD instruction for double-word data that is not located on a double-word
boundary
"
Referencing the kernel address space in User or Supervisor mode
"
Referencing the supervisor space in User mode
"
Referencing an address that does not exist in the kernel, user, or supervisor address space in 64-
bit Kernel, User, or Supervisor mode
"
Branching to an address that is not located on a word boundary
Processing
The common exception vector is used for this exception. The AdEL or AdES code in the Cause register
is set, indicating whether the instruction caused the exception with an instruction reference (AdEL), load
operation (AdEL), or store operation (AdES).
When this exception occurs, the BadVAddr register retains the virtual address that was not properly
aligned or was referenced in protected address space. The contents of the VPN field of the Context
and EntryHi registers are undefined, as are the contents of the EntryLo register.
The EPC register contains the address of the instruction that caused the exception, unless this
instruction is in a branch delay slot. If it is in a branch delay slot, the EPC register contains the address
of the preceding branch instruction and the BD bit of the Cause register is set to 1.
Servicing
The kernel reports the UNIX
exception is usually fatal.
TM
SIGSEGV (segmentation violation) signal to the current process, but the