CHAPTER 5 EXCEPTION PROCESSING
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(2) TLB Invalid exception
Cause
The TLB Invalid exception occurs when a virtual address reference matches a TLB entry that is marked
invalid (the V bit is set to 0). This exception is not maskable.
Processing
The common exception vector is used for this exception. The TLBL or TLBS code in the ExcCode field
of the Cause register is set. If this exception has been caused by an instruction reference or load
operation, TLBL is set. If it has been caused by a store operation, TLBS is set.
When this exception occurs, the BadVAddr, Context, XContext and EntryHi registers contain the virtual
address that failed address translation. The EntryHi register also contains the ASID from which the
translation fault occurred. The Random register normally contains a valid location in which to place the
replacement TLB entry. The contents of the EntryLo register are undefined.
The EPC register contains the address of the instruction that caused the exception unless this
instruction is in a branch delay slot, in which case the EPC register contains the address of the
preceding branch instruction and the BD bit of the Cause register is set to 1.
Servicing
Usually, the V bit of a TLB entry is cleared in the following cases:
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When a virtual address does not exist
"
When the virtual address exists, but is not in main memory (a page fault)
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When a trap is desired on any reference to the page (for example, to maintain a reference bit)
After servicing the cause of a TLB Invalid exception, the TLB entry is located with a TLBP (TLB Probe)
instruction, and replaced by an entry with its Valid bit set to 1.