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CHAPTER 5 EXCEPTION PROCESSING
97
5.3.9 XContext Register (20)
The read/write XContext register contains a pointer to an entry in the kernel page table entry (PTE)
array, an operating system data structure that stores virtual-to-physical address translations. If a TLB
miss occurs, the operating system loads the untranslated data from the PTE into the TLB to handle the
software error.
The XContext register is used by the XTLB Refill exception handler to load TLB entries in 64-bit
addressing mode.
The XContext register duplicates some of the information provided in the BadVAddr register, and puts it
in a form useful for the XTLB exception handler.
This register is included solely for operating system use. The operating system sets the PTEBase field
in the register, as needed. Figure 5-11 shows the format of the XContext register.
Figure 5-11. XContext Register Format
32
4
2
29
29
0
35 34 33
63
4
3
PTEBase
R
BadVPN2
0
PTEBase: The PTEBase field is a read/write field, and is used by software as the pointer to the base
address of the PTE table in the current user address space.
BadVPN2: The BadVPN2 field is written by hardware if a TLB miss occurs. This field holds the value
(VPN2) obtained by halving the virtual page number of the most recent virtual address for
which translation failed.
R:
Space type (00
→
User, 01
→
Supervisor, 11
→
Kernel). The setting of this field matches
virtual address bits 63 and 62.
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
The 29-bit BadVPN2 field has bits 39 to 11 of the virtual address that caused the TLB miss; bit 10 is
excluded because a single TLB entry maps to an even-odd page pair. For a 1-Kbyte page size, this
format may be used directly to address the pair-table of 8-byte PTEs. For 4-Kbyte-or-more page and
PTE sizes, shifting and masking this value produces the appropriate address.