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參數(shù)資料
| 型號(hào)： | DS34S132GN+ |
| 廠(chǎng)商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 121/194頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱(chēng)： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
32 of 194
9.2 TDM Port Functions
The S132 includes 32 TDM Ports. Each TDM Port can be used to support a T1, E1 or any slower TDM data
stream. Each TDM Port uses a serial clock and data interface. The high level functions include:
Structured & Unstructured Formats
T1, E1 and slower TDM Port Line Rates
T1SF, T1ESF and E1 Multi-frame Formats
N x 64 Kb/s PW Packet Payload Rates
With & without CAS Signaling
DS0 Timeslot Assignment
CPU Monitor and Control of CAS Signaling
CPU Control for Data Conditioning
TDM Port Timing
From Recovered or External Time References
Adaptive & Differential Clock Recovery
Generates Differential & Absolute Timestamps
TDM Port, Timeslot and PW Loopbacks
BERT Diagnostics
9.2.1 TDM Port Related Input and Output Clocks
The TDM Port Input and Output Clocks are identified in Figure 9-7.
Figure 9-7. TDM Port Input and Output Clock Overview
DS34S132
CLAD
Ck
Select
Freq
Synthesizer
CLAD
Clock
Select
1.544 MHz
synclk
REFCLK
LIUCLK
2.048 MHz
LCS
LCE
SCS
32 Clock
Recovery
Engines
TDM
Port n
(n = 1 - 32)
EXTCLK0
EXTCLK1
RCLKn
TCLKOn
aclk_n
grclk
32
GRCSS
32
Freq Select
FS[3:0]
CMNCLK
DCR
Common
Clock
High Quality
Reference
(e.g. OCXO)
synclk
_ref_in
The S132 Clock Recovery Engines support “Adaptive Clock Recovery” (ACR) and “Differential Clock Recovery”
(DCR). The ACR technique measures the timing of each successive RXP Packet to determine the recovered clock
frequency. The DCR technique uses RTP timestamps to determine the recovered clock frequency. Two external
clock recovery reference inputs (REFCLK and CMNCLK) are used to supply 1) a Frequency Synthesizer reference
input and 2) to provide a DCR common clock reference.
The Frequency Synthesizer reference input (synclk_ref_in) is required to generate an internal “synclk” signal. To
achieve the jitter/wander performance of ITU G.823/824/8261 the reference should be at least equal to that of a
Stratum 3 clock. The reference can be input on either REFCLK or CMNCLK (selected with G.CCR.SCS). For PSTN
and Cellular Mobile Phone applications, the BITS or GPS Network Timing commonly provide at least a Stratum 3
reference. For applications where a Network Timing reference is not available, then an OCXO may be used. Some
specialized TCXOs can also meet these stringent requirements. Otherwise, if the jitter/wander requirements can be
relaxed then the synclk reference input signal requirements can be equally relaxed.
To support the DCR mode, both ends of the PW must share a common clock reference that is derived from a single
timing source so that the frequency of the common clock reference at both ends of the PW are locked to each
other. The CMNCLK input is used to provide the DCR common clock reference.
In public network applications that use the DCR mode, the public network broadcast Network Timing, that provides
a Stratum 3 or better reference (e.g. BITS or GPS), can be used for the DCR common clock (CMNCLK) input and
the synclk reference input; and the REFCLK input can be tied low to save power.
In applications that use the DCR mode, but the DCR common clock reference is not a Stratum 3 reference (e.g.
private networks), the DCR common clock is connected to the CMNCLK input and a high quality reference (e.g.
OCXO) is connected to the REFCLK input.
In applications that do not use the DCR mode, only a high quality reference is required that can be connected to
CMNCLK or REFCLK and the unused input pin can be tied low to save power.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類(lèi)型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類(lèi)型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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