DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
123 of 194
EB. Field
Name
Addr (A:)
Bit [x:y] Type
Description
BSPR.
A:0408h
BERT Seed / Pattern Register. Default: 0x00.00.00.00
BSP
[31:0] rwc-_-_
BERT Seed/Pattern specifies the seed value for the transmit PRBS pattern, or
the transmit and receive Repetitive Pattern. BSP[31] is the 1st transmitted bit and
the expected 1st receive bit. BSP is ignored when the QRSS Pattern is enabled.
TEICR.
A:0410h
Transmit Error Insertion Control Register. Default: 0x00.00.00.00
RSVD
[31:6]
Reserved.
TEIR
[5:3] rwc-_-_
Transmit Error Insertion Rate specifies the rate at which errors are inserted in
the TXP Packet BERT Generator output data stream (TSEI = 0). One out of every
10k bits is inverted where k = TEIR and k > 0. TEIR = 0 disables the Transmit
Error Insertion Rate function. TEIR = 1 results in every 10th bit being inverted. If
this register is written to during the middle of an error insertion process, the TEIR
insertion rate is updated after the next error is inserted.
BEI
[2] rwc-_-_
Bit Error Insertion Enable = “0” disables error insertion (disables TEIR & TSEI)
TSEI
[1] rwc-_-_
Transmit Single Error Insert A 0 to 1 transition forces a single bit error in the
TXP Packet BERT Generator output stream (TEIR = 0). If this bit transitions more
than once between error insertion opportunities, only one error will be inserted.
MEIMS
[0] rwc-_-_
Reserved.
BSR.
A:0414h
BERT Status Register. Default: 0x00.00.00.00
RSVD
[31:2]
Reserved.
BEC
[1] ros-_-i3
Performance Monitoring Update Status = “1” indicates the TXP TDM BERT
Monitor bit error count > 0 (EB.RBECR.BEC).
OOS
[0] ros-_-i3
Out Of Synchronization = “1” indicates the TXP TDM BERT Monitor is not
synchronized to the incoming pattern.
BSRL.
A:0418h
BERT Status Register Latch. Default: 0x00.00.00.00
RSVD
[31:3]
Reserved.
BEL
[2] rls-crw-i3
Bit Error Latched = “1” when one or more bit errors are detected.
BECL
[1] rls-crw- i3
Bit Error Count Latched = “1” when EB.BSR.BEC transitions from 0 to 1.
OOSL
[0] rls-crw- i3
Out Of Synchronization Latched = “1” when EB.BSR.OOS changes state.
BSRIE.
A:041Ch
BERT Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:3]
Reserved.
BEIE
[2] rwc-_-i3
Bit Error Interrupt Enable. The combination of BEIE = 1 and EB.BSRL.BEL = 1
forces G.GSR1.EBS = 1.
BECIE
[1] rwc-_-i3
Bit Error Count Interrupt Enable. The combination of BECIE = 1 and
EB.BSRL.BECL = 1 forces G.GSR1.EBS = 1.
OOSIE
[0] rwc-_-i3
Out Of Synchronization Interrupt Enable. The combination of OOSIE = 1 and
EB.BSRL.OOSL = 1 forces G.GSR1.EBS = 1.
RBECR. A:0420h
Receive Bit Error Count Register. Default: 0x00.00.00.00
RSVD
[31:24]
Reserved.
BEC
[23:0] rcs-cor-sc
Bit Error Count = # bit errors during the previous update period (EB.BCR.LPMU)
but not including errors during an Out of Sync condition (EB.BSR.OOS = 1).
RBCR.
A:0424h
Receive Bit Count Register. Default: 0x00.00.00.00
BC
[31:0] rcs-cor-sc
Bit Count = # received bits during the previous update period (EB.BCR.LPMU)
but not including errors during an Out of Sync condition (EB.BSR.OOS = 1).
TSTCR.
A:0430h
Test Control Register. Default: 0x00.00.00.00
RSVD
[31:0]
Reserved.