- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1916 > DS34S132GN+ (Maxim Integrated Products)IC TDM OVER PACKET 676-BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | DS34S132GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 141/194頁 |
| 文件大小： | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱： | 90-34S13+2N0 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁當(dāng)前第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁
DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
50 of 194
The Jitter Buffer Maximum Fill Level generally determines the maximum delay. Although the fill level will initially
stabilize at a level just high enough to support the Total PDV, when anomalies occur (e.g. temporary line failures
and RXP PW protection switching) the Jitter Buffer can fill beyond the “Total PDV” level. If the Jitter Buffer fill level
is not “corrected” after an anomaly, because of the near constant rate of the transmit TDM Port, the “extra” data will
not dissipate and will increase the total delay. For example if the Maximum Fill Level is programmed to 1 second
(MJBS or JBMD), and the Total PDV is 10 ms, initially the Jitter Buffer may stabilize at a 10 ms level. But anomalies
could cause the Jitter Buffer to fill beyond the 10 ms level (e.g. equipment programming changes) and as more
anomalies occur, the fill level could accumulate to any level up to 1 second.
There are several registers that the CPU can use to monitor the Jitter Buffer Fill level. Monitoring can be
implemented by polling the Jitter Buffer Maximum and Minimum fill levels or by monitoring for Overrun/Underrun
event indications (data discarded or dummy data inserted). The Jitter Buffer Fill Levels can help to identify setup
errors. Other Jitter Buffer functions that can be enabled include Packet Reordering (for packets received out of
order), packet discard monitoring for too early, too late and duplicate packet Sequence Number. The registers that
support these Jitter Buffer functions include: G.GCR.IPSE, G.GCR.RDPC, G.GSR1.JBS, G.GSRIE1.JBUIE,
G.GSR6.JBGS, PC.CR1.DPDE, B.BCDR1.SCSNRE, B.BDSRL1.JBLPDSL, B.BDSR2 - B.BDSR3, B.BDSR5 -
B.BDSR7, B.GxSRL, and JB.GxSRL.
A Jitter Buffer overflow can occur for three reasons: the selected Transmit TDM Port clock is not the same rate as
that used by the RXP packets (i.e. the wrong clock was selected); clock recovery is selected but has not yet fully
converged to the RXP Packet data rate and is running too slow; the Jitter Buffer depth is too small to handle the
maximum incoming PDV.
The Jitter Buffer is also used by HDLC Connections. However, HDLC Connections, in general, do not transport
constant bit rate data streams (unlike SAT/CES Payload Connections), so the Jitter Buffer is instead used as a
more simplistic FIFO. The Jitter Buffer PDVT and MJBS settings, and the Packet Reordering, Early/Late and
Duplicate Discard functions do not have any meaning with HDLC Connections. HDLC data is forwarded as soon as
it is available. JBMD defines the depth of the FIFO.
9.2.6 TDM Diagnostic Functions
The S132 supports TDM Loopback and TDM BERT Functions for diagnostic testing of the TDM Ports.
9.2.6.1 TDM Loopback
The S132 supports 3 types of Loopbacks for the TDM Ports: TDM Port Line Loopback, TDM Port Timeslot
Loopback and Bundle Loopback. Any number of TDM Ports can be in loopback at the same time.
The TDM Port Line Loopback is enabled using Pn.PTCR2.PRPTLL. This loopback takes data from RDAT and re-
transmits that data on TDAT. All data that is received on RDAT is looped back to TDAT.
The TDM Port Timeslot Loopback is enabled using Pn.PTCR3.PRPTTSL (32 bits, one for each TDM Port
Timeslot). This loopback also takes data from RDAT and re-transmits that data on TDAT, but only for those
Timeslots that have the loopback function enabled. Timeslots that do not have the loopback function enabled
continue to pass data (from Receive TDM Port to TXP Packet and from RXP packet to transmit TDM Port).
For either of these loopbacks to function properly the programmed Transmit TDM Port clock and synchronization
sources (when applicable) must be set to be the same as that of the Receive TDM Port.
When either loopback is enabled, the data for receive TDM Timeslots, that are in loopback, will continue to be
transmitted in TXP packets if TXP Bundles are assigned to the Receive TDM Port and enabled. The TXP packet
stream can be disabled by de-activating the Bundle or by disabling TXP Bundle transmission (B.BCDR3.TXPMS).
RXP Packet data that is received for Timeslots that are in loopback is still forwarded to the Jitter Buffer and is still
used for Clock Recovery. When the loopback is removed, any data that is waiting in the Jitter Buffer is forwarded to
the TDM Port. To prevent the Jitter Buffer from filling with data during a loopback, the payload data for a Bundle
can be discarded (B.BCDR4.RXBDS). Clock Recovery will continue to function for an RXP Bundle that is in one of
these 2 loopbacks as long as the Bundle is selected for Clock Recovery (B.BCDR4.PCRE).
The Transmit TDM Port can only use one timing source, so caution must be exercised when enabling loopbacks for
some Timeslots while other Timeslots are not in loopback. A frequency difference between the looped back RDAT
data and the (non-looped) RXP Packet data will result in occasional slips (corrupted data).
These 2 loopbacks are depicted in Figure 9-17 using a T1/E1 example. The arrow depicts the loopback direction.
The diagram does not depict how “normal” data continues to be forwarded to/from the Ethernet Phy.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS34T102GN+ | IC TDM OVER PACKET 484TEBGA |
| DS3501U+H | IC POT NV 128POS HV 10-USOP |
| DS3502U+ | IC POT DGTL NV 128TAP 10-MSOP |
| DS3503U+ | IC POT DGTL NV 128TAP 10-MSOP |
| DS3897MX | IC TXRX BTL TRAPEZIODAL 20-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。