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參數(shù)資料
| 型號(hào)： | DS34S132GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 138/194頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
48 of 194
The PDVT setting specifies how much data must be stored by the Jitter Buffer before “play-out” (FIFO read) begins.
After “play-out” begins the Jitter Buffer will continue to supply data until the Jitter Buffer is empty. If the Jitter Buffer
empties, then the Jitter Buffer must again fill to the PDVT level before data will again be forwarded.
The MJBS watermark can be used to indicate when the level of stored data exceeds an “expected” maximum
(overrun) level. This can be used to monitor for “unexpected” fill levels (e.g. too much data accumulated because of
improperly configured input or output clocks or if the MJBS setting does not allow for the maximum PDV). MJBS
can be monitored to implement a discard process that prevents each Bundle’s Jitter Buffer from over-filling and
adding to the latency of the data (some Clock Recovery Engine firmware revisions may include a function to
discard Jitter Buffer data when MJBS indicates the Jitter Buffer has too much data). The MJBS register should be
programmed to a level that is lower than the JBMD level so that an MJBS Overrun condition can be detected before
JBMD discarding begins. Figure 9-16 depicts the relationship between the JBMD, MJBS and PDVT settings (the
blue area depicts data that is stored in the Jitter Buffer FIFO).
Figure 9-16. Bundle Jitter Buffer FIFO
MJBS
PDVT
JBMD
This area is empty and
can store SAT/CES TDM
Data from RXP packets.
This area is filled with
SAT/CES TDM Data that
is waiting to be transmited
on the TDM line.
If the SAT/CES TDM Data exceeds the
MJBS Watermark, a Jitter Buffer
Overrun event is counted
(B.BDSR2.JEBEC).
SAT/CES TDM Data is not forwarded to
the TDM Line until the fill level exceeds
the PDVT Watermark.
If the SAT/CES TDM Data exceeds the
JBMD level data, new data is discarded.
Bundle Jitter Buffer FIFO
New SAT/CES packet data is stored here
SAT/CES data is read out from here and sent to TDM Port
The purpose of the Jitter Buffer is to store data that can be transmitted during time periods when the S132 must
wait for a packet that has been “delayed”. At the receiving end of a PW, when a packet is received the PW end
point cannot know whether the PDV for that packet was “zero”, the maximum PDV value or any value in between.
If the receiving PW end point knew that the PDV for a received packet was zero, then the best situation would be to
begin storing data and not forward that data until a time period equal to the maximum PDV. Or, if the PW end point
instead knew that a packet was received with the maximum PDV, then the best situation would be to immediately
forward the data (data will never come later than the maximum PDV; storing would add unnecessary delay).
However the PW end point does not know the PDV level for each packet and thereby must make an assumption.
There are three approaches for setting the PDVT and MJBS values. Each system should be analyzed to determine
which approach is preferred. In each of these approaches the minimum Jitter Buffer delay is equal to the PDVT
setting, while the maximum Jitter Buffer delay (maximum fill level) is either equal to the MJBS or JBMD setting
(MJBS is the maximum if MJBS is monitored as a watermark for discarding; otherwise the maximum is JBMD).
The first approach assumes that it is important to never discard data. This approach results in “2 * Total PDV” ≤
“Jitter Buffer Delay” ≤ “MJBS or JBMD”. This may be the most commonly used setting for existing/installed TDM
over PW services. The settings for this approach are specified by the following equations:
PDVT1 (in ms) = 2 * Total PDV (in ms)
MJBS1 (in ms) = PCT (in ms) + 2 * Total PDV (in ms)
The PCT value is included as part of the MJBS setting to provide a watermark condition that is slightly higher than
the PDVT (playout) watermark and because the originating and terminating ends of the PW cannot be perfectly
phase synchronized together. When the PCT is included as part of the MJBS value, in most cases, the S132 fixed
circuit processing delays can be disregarded (included as part of the PCT value, e.g. BFD PDV).
The second approach assumes that delay must be minimized and only a small amount of discarding should be
allowed. This approach results in a temporary, maximum latency = “2 PDV + PCT”. But as the PDV varies from its
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| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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