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| 型號(hào)： | DS34S132GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 158/194頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
66 of 194
The CPU process of Reading the RXP CPU packets can be polling based using the EMA.RSR1.RFRS status bit or
interrupt driven using the EMA.RSRL1.RFRSL (latched status) and EMA.RSRIE1.RFRIE (Interrupt enable) register
bits. When the CPU detects that a packet is waiting in the RXP CPU FIFO, the CPU must specify the read
operation (EMA.RCR.RPCRC = 110b), specify the read transfer length in Dwords (EMA.RCR.TL) and then begin
reading the data at EMA.RDR.EMRD. The EMA.RCR.TL value specifies how many Dwords are transferred from
the RXP CPU Queue to the RXP CPU FIFO.
The smallest possible RXP Packet Read is 19 Dwords for a 64-byte Ethernet Packet with the 4-byte FCS removed,
3-Dword Header Descriptor and 2-byte Dummy Fill appended to the beginning of the packet. The initial Transfer
Length for each packet can be any value from 1 to 18. The first Dword of the Header Descriptor that is Read by the
CPU identifies the length of the RXP CPU Packet. This is used to determine how many remaining Dwords must be
transferred from the RXP CPU Queue to the RXP CPU FIFO and then Read by the CPU. Each successive Read
Transfer at EMA.RDR.EMRD causes the S132 to update the register with the next Dword in the RXP CPU FIFO.
The EMA.RSR1, EMA.RSR2, EMA.RSRL1 and EMA.RSRIE1 registers provide other control and status bits for the
SDRAM RXP CPU Queue and the RXP CPU FIFO.
9.4.2 TXP CPU Packet Interface
The CPU writes each TXP CPU packet into an S132 staging TXP CPU FIFO and then controls the Writing
(transfer) of the packet to the TXP CPU Queue in the SDRAM. The TXP CPU FIFO can hold 1 packet. The TXP
CPU Queue can hold up to 512 packets. The S132 transmits each packet in the TXP CPU Queue when the
Ethernet Port is not busy transmitting PW packets.
The TXP CPU packets from the CPU must include all of the fields that will be transmitted at the Ethernet Port
including the Ethernet and Application Headers, but not including the Ethernet FCS. Each TXP CPU packet can be
2 Kbytes in length. The CPU must also append a TXP Header Descriptor to the beginning of each packet with
information about the packet. The format of the packet and TXP Header Descriptor are provided in Figure 9-27.
Figure 9-27. Stored TXP CPU Packet and Header Descriptor
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
0 9 8 7 6 5 4 3 2 1 0
1 Dword - Header Control
2-bytes of Dummy Fill = 0x00.00
Entire TXP CPU packet from …
… the Ethernet Destination Address to the end of Ethernet Payload but not including the Ethernet FCS
The TXP CPU Header Control is a single 32-bit Dword as depicted in Table 9-15.
Table 9-15. TXP CPU Header Control
Field
Bit [x:y] Description
TXPLEN [31:21]
TXP Packet Length. The length (in bytes) of the complete TXP CPU Packet from the
Ethernet DA to the end of the Ethernet Payload (not including the Ethernet FCS).
TXOTSO [20:12]
TXP OAM Timestamp Offset = Dword position for TXP OAM Timestamp in Ethernet packet.
TXOTSO = (“Timestamp starting byte position in Ethernet packet” - 2) ÷ 4
TXOTSE [11]
TXP OAM Timestamp Enable. 1 = insert TXP OAM Timestamp; 0 = disabled.
TXAOFF [10:6]
TXP UDP/IP Application Offset = Dword position of IP Header in Ethernet packet.
TXAOFF = (“IP Header starting byte position in Ethernet packet” - 2) ÷ 4
TXUDP
[5]
TXP UDP Header FCS Modify Enable. 1 = insert UDP FCS (only valid if TXIPV4 = 1 or
TXIPV6 = 1).
TXIPV6 [4]
TXP IPv6 Header Exists. 1 = header includes IPv6; 0 = not IPv6.
TXIPV4 [3]
TXP IPv4 Header Exists. 1 = header includes IPv4 (S132 will insert IP FCS); 0 = not IPv4.
RSVD
[2:0]
Reserved.
The S132 can be programmed to add a 32-bit TXP OAM Timestamp to a TXP CPU Packet. One example use for
the TXP OAM Timestamp is described in RFC5087 Appendix D (TDMoIP Performance Monitoring Mechanisms).
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相關(guān)代理商/技術(shù)參數(shù) |
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| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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