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參數資料
| 型號： | DS34S132GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 150/194頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應商設備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
59 of 194
Table 9-9. Malformed PW Header Handling (not including the UDP specific settings)
Test Description
Functional Settings
Special “Fail” Setting
“Fail” Result
Wrong Payload Size
B.BCDR1.PMS,
B.BCDR1.SCSCFPD
-
Discard
RTP Header existence
B.BCDR4.RE
-
Discard
Control Word Header existence
B.BCDR4.CWE
-
Discard
Wrong # L2TPv3 Cookies or MPLS Labels
B.BCDR4.RXLCS
PC.CR1.DPS10
Discard/CPU
The first nibble of the Control Word of a PW packet is used to identify whether the packet payload carries data that
is destined for a TDM Port or that is destined for the CPU (In-band VCCV OAM). When the first nibble is equal to
0x0 the payload is destined for the TDM Port. The Classifier can be programmed to monitor for In-band VCCV
packets by enabling the Control Word monitoring function (B.BCDR4.RXOICWE) and by specifying the Control
Word value that is expected. The commonly used nibble value for (CPU) In-band VCCV packets is 0x1. When
RXOICWE is enabled, the first byte of each received Control Word is compared against PC.CR5.VOV using
PC.CR5.VOM to specify how many bits are to be Masked/Ignored. If the first byte matches VOV and VOM, then the
packet is forwarded to the CPU. If the first byte does not match VOV and VOM, and the first nibble is not 0x0 the
packet is discarded. In-band VCCV can be enabled (per Bundle) for SAT, CES, HDLC and Clock Only Bundles.
If a packet matches all of the Bundle test conditions so far described and has not already been discarded or
forwarded to the CPU, the packet payload/information is forwarded to the HDLC Engine, SAT/CES Engine, Clock
Recovery or CPU. Table 9-10 identifies the register settings that are required for each Connection/Bundle Type that
is listed.
Table 9-10. Bundle Forwarding Options
Connection/Bundle Type
Destination setting
B.BCDR4.RXBDS
Engine Type setting
B.BCDR1.PMT
Clock Recovery setting
B.BCDR4.PCRE
SAT/CES Payload Only
TDM Port
SAT/CES
disable
SAT/CES Payload & PW-Timing
TDM Port
SAT/CES
enable
Clock Only (PW-Timing only)
Discard
SAT/CES
enable
HDLC
TDM Port
HDLC
disable
CPU Debug RXP PW Bundle1
CPU
HDLC or SAT/CES
enable/disable
Note: 1 The SAT/CES and HDLC PW packets can be diverted from their “normal destination” and forwarded to the CPU for
debug purposes by setting the RXBDS to send the packet to the CPU.
The forwarding of payload data for RXP SAT/CES Payload Connections and HDLC Connections can be disabled
using B.BCDR4.RXBDS = 11. When a Payload Connection is disabled and the Jitter Buffer for that Bundle is
empty, the data that is transmitted at the TDM Port is filled with Conditioning Data. The PW-Timing Connection is
disabled using B.BCDR4.PCRE (it is not disabled using B.BCDR4.RXBDS).
Special considerations
Each programmed BID and OAM BID value must be unique across all PW Header types. For example one Bundle
cannot use BID = “17” with UDP and another Bundle use BID = “17” with L2TPv3 (OAM BID = “17” would also not
be allowed). In systems that are unable to co-ordinate the assignment of PW-IDs across all supported PW Header
Types, only one PW Header Type should be used by the S132 to insure unique BIDs and OAM BIDs.
9.3.2.2.3 L-bit Signaling for RXP PWs
The L-bit in the Control Word of a PW packet can be used to indicate across the PSN when a T1/E1 fault has been
detected. The CPU can monitor for received L-bit changes for each RXP Bundle using the G.GCR.LBCDE,
B.G0SRL.CWCDSL - B.G31SRL.CWCDSL, B.G0SRL.CWCDIE - B.G31SRL.CWCDIE, G.GSR5.BGS, G.GSR1.BS
and G.GSRIE1.BIE Registers. This is explained in more detail in the Monitor & Interrupt section.
The S132 can also be programmed to automatically discard the RXP Packet payload when the received L-bit = 1
(invalid payload) and B.BCDR1.LBCAI = 1 (conditioning for L-bit = 1).
9.3.2.3 CPU Packet Classification
Packets that are not identified as PW packets are further processed according to the rules described in this section
to determine whether they are to be sent to the CPU (or discarded). The previously described “send to CPU”
conditions in the “Generalized Packet Classification” and “PW Packet Classification” sections are also repeated in
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| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數據速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數據速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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