DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
84 of 194
G. Field
Name
Addr (A:)
Bit [x:y] Type
Description
EC25
[27] rwc-_-_
Ethernet Clock 25 MHz selects the rate of the ETHCLK input.
0 = ETHCLK is being driven by 125MHz source
1 = ETHCLK is being driven by 25MHz source
ECDC
[26] rwc-_-_
Ethernet Clock DDR SDRAM Clock selects the SDCLK source.
0 = SDCLK is sourced from ETHCLK (125 MHz only; tie DDRCLK low)
1 = SDCLK is sourced from DDRCLK (independent of ETHCLK)
IIM
[25] rwc-_-_
Interrupt Inactive Mode determines the inactive mode of the INT_N pin. The
INT_N pin always drives low when an enabled interrupt source is active.
0 = Pin is high impedance when all enabled interrupts are inactive
1 = Pin drives high when all enabled interrupts are inactive
RDPC
[24] rwc-_-_
Reorder or Duplicate Packet Counters selects which condition increments the
Reorder Counters (see B.BDSR6.SCRPC).
0 = Count the number of reordered good packets
1 = Count the number of duplicate packets
JLPC
[23] rwc-_-_
Jump or Lost Packet Counters selects which condition increments the Jumped
Packet Counters (see B.BDSR5.SCJPC)
0 = Count the jump size for good packets
1 = Count the number of lost packets not received before playout.
IPSE
[22] rwc-_-_
Indicate Playout Start Enable selects which conditions are indicated by the Jitter
Buffer Underrun Status bits (see GxSRL.JBU).
0 = Detect Jitter Buffer Underrun only
1 = Detect Jitter Buffer Underrun and “Start of Playout” changes (monitor
B.BDSR3.JBLL to determine if change is Underrun or Playout)
JBMD
[21:20] rwc-_-_
Jitter Buffer Max Depth = the byte depth for all Jitter Buffers.
0 = 256KB per Jitter Buffer
1 = 128KB per Jitter Buffer
2 = 64KB per Jitter Buffer
3 = 32KB per Jitter Buffer
GRCSS
[19:15] rwc-_-_
Global Recovered Clock Source Select selects which Clock Recovery Engine
(0 – 31) generates the Global Recovered Clock. 0x00 = Clock Recovery Engine 0.
GMMS
[14:12] rwc-_-_
GMII - MII Mode Select selects the Ethernet port mode and interface type.
0 = Ethernet port disabled
2 = Ethernet port enabled using MII interface
3 = Ethernet port enabled using GMII interface
CCOR
[11] rwc-_-_
Clear Counter On Read selects the clear function for the RX Bundle, TX Bundle
and Packet Classifier counters (affects registers with “-cnr-” in the “Type” column).
The counters will roll over after the maximum value.
0 = Counters do not clear
1 = Each Read operation clears the counter
RXHMFIS
[10:8] rwc-_-_
RXP HDLC Minimum Flag Insertion selects minimum number of HDLC flags
that are inserted between HDLC frames at the Transmit TDM Ports. The number
of inserted flags is 1 more than this programmed value (i.e. 0 setting = 1 flag).
OTRS
[7] rwc-_-_
OAM Timestamp Resolution Select selects OAM Timestamps resolution.
0 = 1us OAM Timestamp resolution
1 = 100us OAM Timestamp resolution
LSBCRE
[6] rwc-_-_
Latch Status Bit Clear on Read Enable selects when the latched status register
bits are cleared, but does not apply to the Clock Recovery Status Registers or the
Ethernet MAC Status Registers.
0 = Latched status register bits are cleared when the CPU writes to the register
1 = Latched status register bits are cleared when the CPU reads the register
LBCDE
[5] rwc-_-_
L Bit Change Detect Enable = “1” enables L-bit change detection for all Bundles.
RBCDE
[4] rwc-_-_
R Bit Change Detect Enable = “1” enables R-bit change detection for all
Bundles.