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| 型號(hào)： | DS34S132GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 135/194頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
45 of 194
For RXP Bundles, the S132 monitors the received Control Word L-bit field. If the RXP Bundle is programmed with
B.BCDR1.SCSCFPD = 1 (verify packet size) and the received L-bit = “0” (“PW payload is valid”), the S132 discards
the packet if the PW packet payload size does not match the PMS setting. If SCSCFPD = 1, the received L-bit = 1
(packet payload invalid) and B.BCDR1.LBCAI = 1 (conditioning for L-bit = 1) the PMS setting is ignored.
B.BCDR1.SCSNRE selects whether the packets for RXP SAT/CES Bundles are re-ordered when they are received
out of order. B.BCDR1.RSNS is used to specify whether the Sequence Number in the Control Word or RTP header
is used by this re-ordering function.
A packet is only accepted as a SAT/CES Bundle if the first 4 bits of the Control Word equal 0h. Packet payload
data for RXP SAT/CES Bundles is stored in a Jitter Buffer according to its Sequence Number. When a packet for a
Bundle is “missing” (Sequence Number not received) or the Jitter Buffer underruns, the S132 replaces the missing
data at the transmit TDM Port according to the B.BCDR4.SCLVI setting.
For CES Bundles when B.BCDR4.SCLVI is enabled, the S132 uses the last received byte (Last Value) for each
Timeslot of the Bundle to replace the missing data for up to 375 us. After 375 us, the Conditioning Data selected by
B.BCDR4.RXCOS is inserted. If SCLVI is disabled, the missing data is immediately replaced by Conditioning Data.
For SAT Bundles, the Unstructured format does not identify byte boundaries so the SCLVI function must be
disabled so that Conditioning Data is always used to replace SAT missing data.
9.2.5.2 TDM Port Priority
Each Port can be assigned as “high” or “l(fā)ow” priority, using Pn.PTCR1.DP (TXP direction) and Pn.PRCR1.EP (RXP
direction) so that the SAT/CES/HDLC Engines process some TDM Ports before others. In most applications all
TDM Ports should be assigned the same priority level.
9.2.5.3 Jitter Buffer Settings
The Jitter Buffer provides a means of transitioning TDM data between the PW and TDM domains (RXP direction).
There are 3 fundamental issues when reconstructing a TDM data stream from a stream of packetized data: data
content, delay and frequency. The S132 Jitter Buffer settings are complex so it is important to understand the
parameters that are affected by these settings.
For TDM services, all 3 issues are important. For example, if voice data is delivered error-free, but with 1 second of
delay, then the conversation can be confusing (each person does not know how long to wait to keep from talking
over the other person). A voice connection that adds more than 150 ms of delay is considered a poor connection,
although in unusual cases, up to 400 ms of delay may be accepted. As another example, for PCM voice switching
(e.g. PBX or Class 5 switch), if the reconstructed TDM data is error-free, but the TDM line frequency is not
synchronized to the voice switch, the TDM switching process will corrupt the data. A TDM voice connection is not
significantly affected by a small amount of data corruption, whereas a computer data connection, generally,
depends on almost error-free transmission to minimize the need for re-transmission. All 3 issues are important.
The S132 transmit TDM Port Jitter/Wander performance is affected by the clocking technique that is used. If an
external clock is used, then the S132 Jitter/Wander is primarily determined by the Jitter/Wander of the external
reference. If an internal Clock Recovery Engine is used, then the Jitter (high frequency variation) is determined
from an internal S132 frequency synthesizer that is designed to comply with the TDM Jitter requirements in all
Clock Recovery settings and conditions. The Wander (low frequency variation) is determined by how well the Clock
Recovery Engine can reconstruct the timing of the incoming packet stream. The performance of the Clock
Recovery Wander depends on the maximum excursion and nature of the packet stream PDV, and on the packet
transmission error rate (high packet loss may affect the performance). When it is possible, PWs that are used to
carry Clock Recovery information should be assigned a high priority on the originating PW end point to minimize
the PDV. B.BCDR3.TXBPS can be used to select S132 internal high priority TXP processing and the TXP VLAN
Header P-bits (programmed in the TXP Header Descriptor) can be used to indicate high priority to the network.
The S132 Jitter Buffer smoothes the irregular (bursty) RXP packet rate. The Jitter Buffer stores and then supplies
data as needed according to the transmit TDM Port timing. Because the TDM Port line rate is nearly constant (with
only small variations), the TDM Port cannot significantly slow down or speed up to compensate for too much or too
little stored data. To compensate for the irregular packet rate (burstiness), an infinite depth Jitter Buffer would
insure that data is never lost/discarded, but would also potentially store so much data that the forwarding delay is
too long (potentially making a conversation impossible). A very shallow Jitter Buffer would minimize the delay, but
may not store enough data to prevent a data under-run event (missing data is replaced with dummy data). Each
PW system must determine how to balance these conditions (discard, delay and under-run).
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| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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