參數資料
型號: L64007
廠商: LSI CORP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數: 104/166頁
文件大?。?/td> 1015K
代理商: L64007
Arch
34 Wed May 28 17:36:23 1997
Draft 1/21/97
2-34
Architecture
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
2.4.1MMU
Status Register
The MMU Status Register is a 32-bit register. The MMU Status Low reg-
ister (at address 0xFFFF3) shows the interrupt status PID [15:0] inter-
rupts. The MMU Status High register (at address 0xFFFF4) contains the
interrupt status of PIDs [29:16] in bits [13:0] respectively. Bit [14] is
reserved, and bit [15] contains the status of the adaptation eld MMU
interrupt.
When the host CPU reads either the MMU Status Low register or MMU
Status High register, the register which it reads is reset. It is recom-
mended that both registers be read when servicing the interrupt. If the
host CPU reads and as a result clears either of the registers during the
same clock cycle that new data from a PID is posted, the bit correspond-
ing to that PID is set in the appropriate register and is available during a
subsequent read of that register.
High-speed
Clock
Recovery Unit
High-speed
Interface
Channel
Data Input
Channel
Interface
PID
Processor
Video
Channel
Transport
FIFO
Host Processor
Interface
External
DRAM Memory
Host
Processor
Audio
Clock
Generator
VCxO Clock
VCxO Control
Audio Clock
Decoder
A/V
AUX Port
Channel
FIFO
Decoder
Output Control Unit
(PPU)
8
Audio
Channel
Transport
FIFO
16
8/16
DRAM Control
MMU
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