參數(shù)資料
型號: L64007
廠商: LSI CORP
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 116/166頁
文件大?。?/td> 1015K
代理商: L64007
Arch
45 Wed May 28 17:36:23 1997
Draft 1/21/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
2-45
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
1K locations (0xFFC00 - 0xFFFFF) are reserved for the L64007’s internal
registers. The address space 0x0 - 0xFFBFF is reserved for DRAM
accesses. From the host processor port, the user can program all the
L64007 internal registers and read back the Status Register information.
All internal operations are performed in a 16-bit transfer conguration.
The control signals in the host interface are asynchronous to the chip
clock. They include the following input signals:
Address Strobe signal (AS), which latches the address lines
Chip Select signal (CS), which selects the L64007 in a system
Upper Byte Data Strobe (UDS) and Lower Byte Data Strobe (LDS),
which latch the respective upper and lower byte data
Read or Write signal (R/W), which determines the direction of the
bus cycle
The L64007 outputs feedback to the host processor when it is ready to
complete the cycle with the DTACK signal.
Figure 2.40 and Figure 2.41 show typical 16-bit read and write cycles.
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