參數(shù)資料
型號(hào): L64007
廠商: LSI CORP
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 106/166頁
文件大?。?/td> 1015K
代理商: L64007
Arch
36 Wed May 28 17:36:23 1997
Draft 1/21/97
2-36
Architecture
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
3.
Host processor interface (data for read or write, direct access, or
DMA transfer)
All three data resources can be operated concurrently. Each resource
has its own FIFO used for data communication. Each one can access a
different address in the DRAM. A special-purpose arbitration with priority
logic has been designed to efciently manage the data ow between
these resources and the external DRAM device.
The DRAM controller lets the external host processor access the external
DRAM memory directly. The DRAM controller supports page data trans-
fer between the external DRAM memory and the on-chip Cache memory
in three modes: EDO, Fast, and Slow. The host processor interfaces with
the Cache controller and the Cache memory. The host processor
address is used to determine the page hit or miss, and as a base
address for fetching a page from the DRAM memory. More details about
the direct access operation are in Section 2.5, “Host Processor Interface.”
Figure 2.31 shows the read cycle timing diagram for the DRAM controller
in EDO mode. The low portion of the CAS signal is 0.5 cycles. Data is
latched on the falling edge of CAS.
Figure 2.31
DRAM Controller
Read Timing in
EDO mode
RAS
UCAS
LCAS
WE
OE
DATA
CLK
ADDR
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