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參數(shù)資料
| 型號： | L64007 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 140/166頁 |
| 文件大?。?/td> | 1015K |
| 代理商： | L64007 |
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Draft 1/16/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
3-3
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
CS
Chip Selects
Input
When this signal is LOW, the L64007 is selected for a pri-
mary microprocessor Read or Write cycle, as determined
by the state of R/W signal. When this signal is HIGH, the
L64007 does not respond to the microprocessor address
or data bus, and the data bus lines are in 3-state mode.
D[15:0]
Data Bus
Bidirectional
This 16-bit bus is used to transfer data to and from the
host processor bus. When the L64007 is in a read bus
cycle, this bus is driven by the L64007. When in a write
cycle, this bus is driven by the external host processor
and should be valid on the LOW-to-HIGH transition of the
UDS and LDS signals. When the L64007 is not in a bus
cycle, these lines are 3-stated. After RESET, the bus
automatically switches to 3-state.
DACK
DMA Acknowledge
Input
This active LOW input is used by the host processor or
DMA controller to signal the L64007 that a DMA request
has been granted and the DMA bus operation is in
progress. All other signals on the host processor bus are
ignored. For the L64007, the DMA read or write direction
is determined by programming the TR_DIR bit in the Sys-
tem Mode Register. When in read DMA direction, D[15:0]
are driven by the L64007 with valid data on D[15:0] from
the HIGH-to-LOW transition of DACK as long as it stays
LOW. On the LOW-to-HIGH transition of DACK, the
L64007 assumes the data has been latched and D[15:0]
is 3-stated. During a write DMA operation, data on
D[15:0] is latched on the LOW-to-HIGH transition of the
DACK signal. The L64007 responds to DACK only if the
DREQ signal is also asserted. The LOW-to-HIGH transi-
tion of DACK indicates that the data has been latched.
DREQ
DMA Request
Output
This active LOW output is used by the L64007 to signal
the host processor or external DMA controller that it is
ready for a DMA read or write operation. The activation
and deactivation of this signal are done internally by the
L64007 DMA FIFO control logic. The request activity is
based on a burst-level value that is programmed in the
System Control Register. DREQ is not active if the
TR_EN bit in the System Control Register is reset LOW.
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