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參數(shù)資料
| 型號(hào)： | L64007 |
| 廠商： | LSI CORP |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 141/166頁(yè) |
| 文件大?。?/td> | 1015K |
| 代理商： | L64007 |
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Draft 1/16/97
3-4
Signal Denitions
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
UDS
Upper Byte Data Strobe
Input
When in a write bus cycle, a LOW-to-HIGH transition of
this input indicates that the upper byte data on D[15:8]
has been latched into the L64007 when accessing DRAM
(for register access, D[15:0] is used). When in a read bus
cycle, LOW-to-HIGH transition of this input indicates that
the host processor has latched the upper byte data on
D[15:8].
LDS
Lower Byte Data Strobe
Input
When in a write bus cycle, a LOW-to-HIGH transition of
this input indicates that the lower byte data on D[7:0] has
been latched into the L64007. When in a read bus cycle,
LOW-to-HIGH transition of this input indicates that the
host processor has latched the lower byte data on D[7:0].
DTACK
Data Acknowledge
Output
This active LOW and 3-state output signal is used to
acknowledge data transfer to and from the host processor
bus. It is output driven only when CS is asserted. DTACK
is asserted when the internal L64007 resource signals
that it is ready for the bus cycle to be completed. DTACK
stays LOW until the end of the bus cycle and after UDS,
LDS, and AS have been de-asserted.
INTR
Interrupt
Output
When an internal L64007 interrupt condition occurs, and
this open-drain output signal is unmasked, the INTR line
is driven LOW. When the appropriate internal interrupt
status register is read, the interrupt is cleared automati-
cally.
RESET
Reset
Input
Asserting this active LOW signal resets the L64007 to its
power-on state. To ensure a complete reset of the
L64007, the RESET pulse must be asserted for at least
two Master Clock cycles.
R/W
Read/Write
Input
When this signal is LOW, it indicates an attempt by the
external host processor to write to the L64007. The data
on D[15:0] is latched into the chip on the LOW-to-HIGH
transition of the UDS and LDS signals. When R/W is
HIGH, it indicates an attempt by the external host proces-
sor to read data from the L64007. The L64007 drives
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