參數(shù)資料
型號： L64007
廠商： LSI CORP
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝： PLASTIC, QFP-160
文件頁數(shù)： 155/166頁
文件大?。?/td> 1015K
代理商： L64007
register
7 Wed May 28 17:37:25 1997
Draft 1/21/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
4-7
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
ACT
Active
13
When set to 1, the PPU lters the stream for this PID;
otherwise, it does not.
RES
Reserved
[12:11]
These bits are reserved.
PES/PSI
Packetized Elementary Stream /
Program-Specic Information
10
This bit indicates whether the payload of this PID stream
is of type PES (set to 1) or PSI (set to 0). When PSI is
selected, the L64007 performs section ltering on the
packet payload.
AF
Post AF
9
When set to 1, this bit indicates that adaptation elds
related to this PID are to be posted to the MMU. When
set to 0, adaptation elds related to this PID are not to
be posted.
AUX
Post to AUX Port
8
When set to 1, the transport packet of this PID is posted
to the AUX port. This is done in parallel to the payload
data and adaptation eld of this packet, which are posted
to the external DRAM or host interface according to the
DES control bit. When set to 0, the transport packet of
this PID is not posted to the AUX port.
RES
Reserved
[7:0]
These bits are reserved.
4.2.3
Filter Enable
Register
The L64007 provides 32 sets of programmable lters for section ltering.
Each set of lters consists of a 12-byte matching pattern and a 12-byte
masking pattern. Each lter-enable bit enables the corresponding lter
set to be applied (i.e., bit 31 = ‘1’ enables lter 31; bit 0 = ‘1’ enables
lter 0). All combinations of lter enabling are supported.
FILTER_EN_MSB
Filter Enable MSB
[15:0]
This is the MSB of the 32-bit lter enable register.
15
0
Filter Enable Register (MSB)
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