register
5 Wed May 28 17:37:25 1997
Draft 1/21/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
4-5
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
4.2
PSI/PES PID
Control
Registers
(Group 0)
This group of registers can handle up to 30 concurrently operating PIDs.
Each PID has its own group of registers; each group comprises 16 reg-
isters of 16 bits each. The rst eight registers in the group control the
operation of the PID Processor Unit (PPU) providing the user-program-
mable parameters such as PID value, Active, Enable Interrupt, Section
ltering control elds, etc. The other eight registers in the group control
the operation of the Memory Management Unit (MMU), providing the
user-programmable parameters for the location of the cyclic buffer that
stores the PID payload data. The 30 PSI/PES PID Control registers
occupy memory space from 0xFFC00 to 0xFFDDF.
The L64007 assumes that the payload data for the PIDs in this group is
either of type PES or PSI. The audio or video of the program to be
decoded should not be programmed through this group.
The following sections describe the registers and elds in this group.
4.2.1
PID Value (PID)
This 13-bit register comprises the PID eld. Its structure and bit eld are
described below.
RES
Reserved
[15:14]
These bits are reserved.
CRCE
CRC Enable
13
If this bit is 1, the L64007 enables CRC checking for PSI
sections.
PID
Packet ID
[12:0]
This 13-bit eld determines the value to be compared
with the PID eld transmitted in the transport packet
header. If the PID value matches and the ACT bit is set
to 1, the PPU continues to parse the data in this transport
packet. The following table shows the common use of the
PID eld in MPEG-2 compliant system. This is only an
example; the user can program any value without restric-
tion. Only the null PID, 0x1FFF, causes the L64007 to dis-
card a null packet.
15
14
13
12
0
RES
CRCE
PID