參數(shù)資料
型號: L64007
廠商: LSI CORP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 105/166頁
文件大?。?/td> 1015K
代理商: L64007
Arch
35 Wed May 28 17:36:23 1997
Draft 1/21/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
2-35
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
2.4.2
MMU FIFO
Flush
To eliminate the possiblity of reading spurious data from the DRAM mem-
ory FIFO, that FIFO should be ushed upon deactivating one of the cyclic
buffers.
To implement a FIFO us, the host rst deactivates the PID. Next, the
host programs the syncb_cnt (sync byte count) bit eld in the Channel
Decoder Control Register (CCR), bits [11:9] to a value greater than or
equal to 2 (010 binary).
After syncb_cnt counts down to 0, SCINT is set in the System Status
Register, bit 8, and the host recieves an interrupt. At this point, at least
two packets have entered PID Processor and no residual data of deac-
tivated PID can be inside the PID Processor.
Next, the host sets the MMU ush bit. The host then waits until the MMU
ush bit is reset. At this point, there is no residula data of deactivated
PIDs inside the MMU FIFO. The host can now reprogram the MMU point-
ers.
2.4.3
DRAM
Controller
The DRAM Controller is designed to support an interface to commodity
DRAM devices in a 16-bit bus conguration. It supports three types of
data transfer and three types of page break sizes, allowing for a high
level of exibility in selection of DRAM devices. Supported data transfer
types are:
1.5 Cycle Slow Page Mode
1 Cycle Fast Page Mode
Extended Data Out (EDO)
Supported page break sizes are:
256 words
512 words
1024 words
All these types are user-programmable options.
The DRAM Controller supports three data transfer sources:
1.
PID Post-processor (data for write only)
2.
A/V extended channel buffer (data for read only)
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