參數(shù)資料
型號: L64007
廠商: LSI CORP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 132/166頁
文件大?。?/td> 1015K
代理商: L64007
Arch
60 Wed May 28 17:36:23 1997
Draft 1/21/97
2-60
Architecture
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
allocates eight internal register addresses for accessing the L64002
decoder through the L64007. When the host processor tries to access
the L64002 through the L64007, it activates a normal host bus cycle with
an address that matches one of these eight addresses. Subsequently a
chip select to the L64002 is generated, and data is presented to, or by,
the L64002 device as a response to the read or write cycle. If the L64002
is not ready to complete the host bus cycle, it asserts the AV_WAIT sig-
nal. The L64007 detects the AV_WAIT signal and postpones generation
of the DTACK signal; the AV_WAIT also indicates that the L64002 is
ready to complete the bus cycle.
Figure 2.54 shows the connection between the L64007’s AUX port inter-
face and L64002’s host processor port
Figure 2.54
L64007 and L64002
Connection in Parallel
Mode
AVCLK
Host Processor
Interface
Control
8-Bit Parallel Data Bus
AUXD[7:0]
VVALID
AVALID
VREQ
AREQ
AVERR
AV_CS
AV_WAIT
L64002
SYSCLK
27 MHz
VVALID
DATA[7:0]
AVALID
VREQ
AREQ
ERROR
READ
CS
AS
WAIT
A[2:0]
L64007
AVSD
SERI
SCKLI
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