Arch
26 Wed May 28 17:36:23 1997
Draft 1/21/97
2-26
Architecture
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
The rst and last of these are not practicable. The only alternative is a
partially parallel, partially serial matching process. This means that the
input data ow must be stalled during the serial portion of the matching
process. Consequently, data backs up into the existing channel FIFO.
The number of bytes of data in the input stream that are passed through
the lter affects the amount of backup that can occur.
The lter is implemented by matching each section byte against eight of
the 32 patterns at once. This provides the best compromise between ef-
cient implementation and constraints upon the data stream and other cir-
cuitry.
The following equation calculates the maximum number of sections
allowed per transport packet with the FIFO size in the Channel Decoder
Interface (CDI) for two successive transport packets. This equation
assumes that all packet data must be processed in one packet time; thus
guaranteeing that an increasing backlog does not occur.
The number of sections per packet is:
where
dataRate is the incoming data rate in mega-bits per second. This
equation is valid for data rates up to 216 MBits/s (i.e., one byte per clock
cycle at 27 MHz). For a data rate of 60Mbits per second, this equation
yields 13 sections per transport package.
The section processing and ltering procedure handles all MPEG-2 com-
pliant scenarios. The following are a few examples.
1128
dataRate
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5.2
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