Arch
17 Wed May 28 17:36:23 1997
Draft 1/21/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
2-17
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
Figure 2.14
PID Processor
Architecture Block
Diagram
2.3.1
PID Pre-
processor
The PID Pre-processor lters only those packets matching user-program-
mable PIDs from the transport stream. This block fetches the rst four
bytes from the transport header of each packet (see
Figure 1.1). The
transport header contains the PID value of each packet. The PID Pre-
processor compares the packet PID against the 32 user-programmable
PIDs, starting from PID index address 0 up to PID index address 31.
(The PID addresses are provided in
Chapter 4.) If there is no match, the
PID Pre-processor discards the packet. A transport packet passes the
PID ltering and is posted to the next level of ltering in the PPU only if
it matches one of the user-programmable PIDs (ltered transport pack-
ets).
The following paragraphs briey describe the function of the register le.
PID VALUE - This 13-bit eld in the PID matching register is used for
matching with the PID eld in the transport packets. The L64007 imposes
no restriction on the PID values that can be placed in PID Indexes 0
through 29 except for the value 0x1FFF, which is the null PID and causes
the L64007 to discard the packet. However, ISO-compliant streams
reserve the PID values 0 and 1 for the Program Association Table (PAT)
and for the Conditional Access Table (CAT), respectively.
PID
Register File
Matching
PID
Pre-Processor
Transport In
Attribute
Register File
Control
PID
Post-Processor
Filtered
Transport
PSI / PES
A/V PES
AF
FIFO
from Channel
ACRF
To
MMU
and
Match and Mask
Patterns