參數(shù)資料
型號: L64007
廠商: LSI CORP
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 136/166頁
文件大?。?/td> 1015K
代理商: L64007
Arch
63 Wed May 28 17:36:23 1997
Draft 1/21/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
2-63
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
The host processor controls the audio clock output frequency by pro-
gramming the Frequency Synthesizer Cell (FSC) Control Register and
the FSC Clock Divide Value Register. Both of these registers are write-
only.
Each clock divide value can be programmed by setting the FSC_SEL bit
of the System Mode Register. Since the FSC_SEL bit toggles after each
write of the FSC Clock Divide Value Register, the host does not have to
change the FSC_SEL bit if it writes both clock divide values consecu-
tively. The following sample shows how the host can program the audio
clock registers:
1.
Program the FSC Clock Divide Value Register with a reference clock
divide value.
2.
Program the FSC Clock Divide Value Register with a DCO clock
divide value.
3.
Program the FSC Control Register with 0x2501.
The selected audio clock frequency depends on both the sampling rate
of the source material and the oversampling frequency (fo) of the PCM
18-bit DAC
IREF
DAC
Controlled
Oscillator
Digital
FSC
ACLK
REF_DIV
18
16
27 MHz
FSC_CNTL
14
DCO_DIV
16
0.1
F
L64007
VDD
16,840
±1%
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