參數(shù)資料
型號: L64007
廠商: LSI CORP
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 37/166頁
文件大小: 1015K
代理商: L64007
register
49 Wed May 28 17:37:25 1997
Draft 1/21/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
4-49
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
4.10.6
Extension
Register (ER)
The ER determines the 5 LSBs of the WAR and the LAR or RAR. These
5 LSBs and the 16 MSBs form a complete 21-bit register address value.
Each 5-bit nibble corresponds to a different register.
Note that the ER can be accessed only after a read to the WAR or LAR.
Since the WAR can be changed by the internal hardware between host
reads of the WAR, LAR, and ER, the WAR_LSB or LAR_LSB is locked
into a ip-op when the WAR or LAR is being accessed. This guarantees
that the full WAR, LAR, or ER value read is isotropic.
0
Zero
[15:13], [7:5]
WAR_LSB
Write Address LSB Register
[12:8]
The WAR_LSB bits are concatenated with the
WAR_MSB to form a 21-bit address pointer.
LAR_LSB/
Last/Read Address LSB Register
[4:0]
RAR_LSB
For the ERs in Group 0, the LAR_LSB bits are concate-
nated with the LAR_MSB to form a 21-bit address
pointer. For the ERs in Groups 1 and 2, the RAR_LSB
bits are concatenated with the RAR_MSB to form a 21-
bit address pointer.
15
13 12
8
7
5
4
0
WAR_LSB
0
LAR_LSB
For Group 0
0
WAR_LSB
0
RAR_LSB
For Groups 1 and 2
WAR_LSB
Write Address LSB Location
0x0
0
0x1
1
0x2
2
.
0xF
15
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