Arch
55 Wed May 28 17:36:23 1997
Draft 1/21/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
2-55
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
Data is transferred to the port through an on-chip pair of 512-byte-deep
FIFOs. This feature supports the MPEG-2 system layer requirement,
dedicating a 512-byte transport buffer to each one of the PES elementary
streams. This feature makes it possible for low-cost applications to use
the device without needing external DRAM memory. The chip can handle
three back-to-back packets coming to the channel at 60 Mbits/s. The
architecture allocates one transport buffer’s FIFO to serve PES data
coming on PID Index 30 (audio), and the other to serve data coming on
PID Index 31 (video).
In normal operation, the output data from the PID Post-processor is
transferred directly to the transport buffers’ FIFOs. Some applications,
however, allow using the extended channel mode option; this routes PES
streams coming on PID Index 30 and PID Index 31 rst to the external
DRAM, and then to the transport buffer FIFOs (see
Figure 2.50). This is
very useful for systems with much jitter in the data transfer rate. You must
allocate buffer space in the memory for the extra data.
High-speed
Clock
Recovery Unit
High-speed
Interface
Channel
Data Input
Channel
Interface
PID
Processor
Video
Channel
Transport
FIFO
DRAM Control
MMU
Host Processor
Interface
External
DRAM Memory
Host
Processor
Audio
Clock
Generator
VCxO Clock
VCxO Control
Audio Clock
Decoder
A/V
AUX Port
Channel
FIFO
Decoder
Output Control Unit
(PPU)
8
Audio
Channel
Transport
FIFO
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