參數(shù)資料
型號: L64007
廠商: LSI CORP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 115/166頁
文件大?。?/td> 1015K
代理商: L64007
Arch
44 Wed May 28 17:36:23 1997
Draft 1/21/97
2-44
Architecture
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
even host address selects set zero, and an odd host address selects
set one. If the second bit of the host address is 1, the host processor
accesses the TAG data. If this bit is 0, the host processor accesses
the control data.
DRAM direct. In this mode, the host bypasses the Cache and
accesses the DRAM directly.
2.5
Host Processor
Interface
The L64007 host processor interface is designed to support a variety of
standard microprocessors, mainly of the Motorola 68xxx microprocessor
families. The L64007 can support an 8- or 16-bit host processor data bus
width (see Figure 2.39).
Figure 2.39
L64007 Architecture
Block Diagram
The host processor interface supports a 20-bit address bus; thus, up to
1M 16-bit words can be directly accessed by the host processor. The last
High-speed
Clock
Recovery Unit
High-speed
Interface
Channel
Data Input
Channel
Interface
PID
Processor
Video
Channel
Transport
FIFO
DRAM Control
MMU
External
DRAM Memory
Host Processor
Audio
Clock
Generator
VCxO Clock
VCxO Control
Audio Clock
Decoder
A/V
AUX Port
Channel
FIFO
Decoder
Output Control Unit
(PPU)
8
Audio
Channel
Transport
FIFO
16
8/16
Host Processor
Interface
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