MOTOROLA
MC68307 USER’S MANUAL
9-1
SECTION 9
IEEE 1149.1 TEST ACCESS PORT
The MC68307 includes dedicated user-accessible test logic that is fully compatible with the
IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems asso-
ciated with testing high-density circuit boards have led to development of this standard
under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action
Group (JTAG). The MC68307 implementation supports circuit-board test strategies based
on this standard.
The test logic includes a test access port (TAP) consisting of five dedicated signal pins, a
16-state controller, an instruction register, and four test data registers. A boundary scan reg-
ister links all device signal pins into a single shift register. The test logic, implemented using
static logic design, is independent of the device system logic. The MC68307 implementation
provides the following capabilities:
1. Perform boundary scan operations to test circuit-board electrical continuity
2. Sample the MC68307 system pins during operation and transparently shift
out the result in the boundary scan register
3. Bypass the MC68307 for a given circuit-board test by effectively reducing the bound-
ary scan register to a single bit
4. Disable the output drive to pins during circuit-board testing
5. Drive output pins to stable levels
NOTE
Certain precautions must be observed to ensure that the IEEE
1149.1 test logic does not interfere with non-test operation. See
9.1 OVERVIEW
NOTE
This description is not intended to be used without the support-
ing IEEE 1149.1 document.
The discussion includes those items required by the standard and provides additional infor-
mation specific to the MC68307 implementation. For internal details and applications of the
standard, refer to the IEEE 1149.1 document.
An overview of the MC68307 implementation of IEEE 1149.1 is shown in
Figure 9-1. The
MC68307 implementation includes a 16-state controller, a 4-bit instruction register, and four
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