System Integration Module
MOTOROLA
MC68307 USER’S MANUAL
5-29
is first to set the LPEN bit and then to issue a STOP instruction immediately to place the
processor in a known state.
0 =The CPU clock is to be maintained at the programmed frequency.
1 =The CPU should be shut down as the following STOP instruction is executed. The
sleep/wake-up logic coordinates the re-awakening operation when it receives an
interrupt from any source. The STOP instruction should unmask all interrupts so
that the processor will exit from the STOP on wakeup.
After either cold reset or wakeup, this bit is cleared in hardware, and so the processor
clock runs. Note that for minimum power consumption, any unused peripherals can have
their clocks stopped as well, using the UACD, MBCD, CKD and TMCD bits. All these bits
CDEN—Clock Divider Enable
Setting this bit allows the internal clock signal for the EC000 core processor to be reduced
in frequency as programmed in the CD2–CD0 bits.
0 =The CPU clock is to be maintained at the full operating frequency of the system clock
input.
1 =The CPU clock should be maintained with a reduced frequency as programmed in
the clock divider bits (CD2–CD0).
After a cold reset, this bit is cleared, so the EC000 core runs at full speed. This bit is un-
affected by a wake-up, hence if the EC000 core enters sleep mode with a reduced clock
frequency it will wake-up with the same reduced clock frequency. Note that the LPEN bit
always overrides the CDEN/CD2–CD0 setting.
CKD—Clock-Output Disable
This bit allows the MC68307 CLKOUT pin to be disabled after reset, if it is not required
externally. Turning this driver off effectively saves power and reduces potential RFI prob-
lems.
0 = The CLKOUT pin is enabled. The system clock frequency is available.
1 = The CLKOUT pin is disabled, and is driven permanently high.
After cold reset, this bit defaults to zero, thus the CLKOUT pin is active.
EBUSW—Bus Width for Non-Chip-Select Cycles with External DTACK
This bit defines the data bus width (port size) for bus cycles which do not match any of the
programmable chip selects or internal locations, and therefore require an external DTACK
to terminate the cycle.
0 = The bus width for non-chip-selected memory accesses is 8-bits.
1 = The bus width for non-chip-selected memory accesses is 16-bits.
After cold reset, this bit defaults to one, so the default width for non-chip-selected memory
accesses is 16-bits.
Bit 3—Reserved by Motorola
This control bit is as yet undefined, and may be used for Motorola internal test or for future
derivative products. Leave its value as zero always.