- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45211 > MC68307CFG16 (MOTOROLA INC) 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | MC68307CFG16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 77/264頁 |
| 文件大?。?/td> | 949K |
| 代理商： | MC68307CFG16 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁當前第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁
Serial Module
8-8
MC68307 USER’S MANUAL
MOTOROLA
8.3.2.2 RECEIVER. The receiver is enabled through its UCR located within the serial mod-
ule. Functional timing information for the receiver is shown in Figure 8-6. The receiver looks
for a high-to-low (mark-to-space) transition of the start bit on RxD. When a transition is
detected, the state of RxD is sampled each 16
× clock for eight clocks, starting one-half clock
after the transition (asynchronous operation) or at the next rising edge of the bit time clock
(synchronous operation). If RxD is sampled high, the start bit is invalid, and the search for
the valid start bit begins again. If RxD is still low, a valid start bit is assumed, and the receiver
continues to sample the input at one-bit time intervals, at the theoretical center of the bit,
until the proper number of data bits and parity, if any, is assembled and one stop bit is
detected. Data on the RxD input is sampled on the rising edge of the programmed clock
source. The least significant bit is received first. The data is then transferred to a receiver
holding register, and the RxRDY bit in the USR is set. If the character length is less than
eight bits, the most significant unused bits in the receiver holding register are cleared.
After the stop bit is detected, the receiver immediately looks for the next start bit. However,
if a non-zero character is received without a stop bit (framing error) and RxD remains low
for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new
start bit is detected. The parity error (PE), framing error (FE), overrun error (OE), and
received break (RB) conditions (if any) set error and break flags in the USR at the received
character boundary and are valid only when the RxRDY bit in the USR is set.
If a break condition is detected (RxD is low for the entire character including the stop bit), a
character of all zeros is loaded into the receiver holding register, and the RB and RxRDY
bits in the USR are set. The RxD signal must return to a high condition for at least one-half
bit time before a search for the next start bit begins.
The receiver detects the beginning of a break in the middle of a character if the break per-
sists through the next character time. When the break begins in the middle of a character,
the receiver places the damaged character in the receiver first-in-first-out (FIFO) stack and
sets the corresponding error conditions and RxRDY bit in the USR. Then, if the break per-
sists until the next character time, the receiver places an all-zero character into the receiver
FIFO and sets the corresponding RB and RxRDY bits in the USR.
8.3.2.3 FIFO STACK. The FIFO stack is used in the UART's receiver buffer logic. The stack
consists of three receiver holding registers. The receive buffer consists of the FIFO and a
receiver shift register connected to the RxD (refer to Figure 8-4). Data is assembled in the
receiver shift register and loaded into the top empty receiver holding register position of the
FIFO. Thus, data flowing from the receiver to the CPU is quadruple buffered.
In addition to the data byte, three status bits, PE, FE, and RB, are appended to each data
character in the FIFO; OE is not appended. By programming the ERR bit in the channel's
mode register (UMR1), status is provided in character or block modes.
The RxRDY bit in the USR is set whenever one or more characters are available to be read
by the CPU. A read of the receiver buffer produces an output of data from the top of the FIFO
stack. After the read cycle, the data at the top of the FIFO stack and its associated status
bits are 'popped', and new data can be added at the bottom of the stack by the receiver shift
相關PDF資料 |
PDF描述 |
|---|---|
| MC68307PU16 | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| MC68307PU16V | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| MC68307FG16 | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| MC68322FT16 | 16-BIT, 16.667 MHz, RISC PROCESSOR, PQFP160 |
| MC68331CFC20B1 | 32-BIT, 20 MHz, MICROCONTROLLER, PQFP132 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC68307UM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor |
| MC68307V | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor |
| MC68322 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Printer Processor |
| MC68322AD | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Printer Processor |
| MC68322FT20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。