MOTOROLA
MC68307 USER’S MANUAL
vii
TABLE OF CONTENTS
Section 1
Introduction
1.1
M68300 Family ............................................................................................. 1-3
1.1.1
Organization ............................................................................................... 1-3
1.1.2
Advantages ................................................................................................. 1-3
1.2
MC68307 Architecture .................................................................................. 1-4
1.2.1
EC000 Core Processor ............................................................................... 1-4
1.2.2
System Integration Module (SIM07) ........................................................... 1-4
1.2.2.1
External Bus Interface .............................................................................. 1-5
1.2.2.2
Chip Select And Wait State Generation ................................................... 1-5
1.2.2.3
System Configuration and Protection ....................................................... 1-5
1.2.2.4
Parallel Input/Output Ports ....................................................................... 1-5
1.2.2.5
Interrupt Controller.................................................................................... 1-6
1.2.3
Timer Module .............................................................................................. 1-6
1.2.4
UART Module ............................................................................................. 1-6
1.2.5
M-Bus Module............................................................................................. 1-6
1.2.6
Test Access Port......................................................................................... 1-7
Section 2
Signal Description
2.1
Bus Signals ................................................................................................... 2-5
2.1.1
Address Bus (A23–A0) ............................................................................... 2-5
2.1.1.1
Address Bus (A23–A8) ............................................................................. 2-5
2.1.1.2
Address Bus (AD7–AD0) .......................................................................... 2-5
2.1.2
Data Bus (D15–D0) .................................................................................... 2-6
2.2
Chip Selects.................................................................................................. 2-6
2.2.1
Chip Select 0 (CS0) .................................................................................... 2-6
2.2.2
Chip Select 1 (CS1) .................................................................................... 2-6
2.2.3
Chip Select 2 (CS2, CS2B, CS2C, CS2D) ................................................. 2-6
2.2.4
Chip Select 3 (CS3) .................................................................................... 2-7
2.3
Bus Control Signals ...................................................................................... 2-7
2.3.1
Data Transfer Acknowledge (DTACK) ........................................................ 2-7
2.3.2
Address Strobe (AS) ................................................................................... 2-8
2.3.3
Read/Write (R/W) ....................................................................................... 2-8
2.3.4
Data Strobes, Upper and Lower (UDS, LDS) ............................................. 2-8
2.3.5
8051 Address Latch Enable (ALE) ............................................................. 2-9
2.3.6
8051-Compatible Bus Read (RD) ............................................................... 2-9
2.3.7
8051-Compatible Bus Write (WR) .............................................................. 2-9
2.3.8
Bus Width Select for CS0 (BUSW0) ........................................................... 2-9
2.4
Exception Control Signals............................................................................. 2-9
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