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參數(shù)資料
| 型號(hào)： | MC68307CFG16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 257/264頁(yè) |
| 文件大?。?/td> | 949K |
| 代理商： | MC68307CFG16 |
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EC000 Core Processor
4-16
MC68307 USER’S MANUAL
MOTOROLA
the spurious interrupt vector instead of the bus error vector. The processor then proceeds
with the usual exception processing.
4.6.5 Instruction Traps
Traps are exceptions caused by instructions; they occur when a processor recognizes an
abnormal condition during instruction execution or when an instruction is executed that nor-
mally traps during execution.
Exception processing for traps is straightforward. The status register is copied; the supervi-
sor mode is entered; and tracing is turned off. The vector number is internally generated; for
the TRAP instruction, part of the vector number comes from the instruction itself. The pro-
gram counter, and the copy of the status register are saved on the supervisor stack. The
saved value of the program counter is the address of the instruction following the instruction
that generated the trap. Finally, instruction execution commences at the address in the
exception vector.
Some instructions are used specifically to generate traps. The TRAP instruction always
forces an exception and is useful for implementing system calls for user programs. The
TRAPV and CHK instructions force an exception if the user program detects a run-time
error, which may be an arithmetic overflow or a subscript out of bounds. A signed divide
(DIVS) or unsigned divide (DIVU) instruction forces an exception if a division operation is
attempted with a divisor of zero.
4.6.6 Illegal and Unimplemented Instructions
Illegal instruction is the term used to refer to any of the word bit patterns that do not match
the bit pattern of the first word of a legal processor instruction. If such an instruction is
fetched, an illegal instruction exception occurs. Motorola reserves the right to define instruc-
tions using the opcodes of any of the illegal instructions. Three bit patterns always force an
illegal instruction trap on all M68000 family-compatible microprocessors. The patterns are:
$4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA and $4AFB, are reserved for
Motorola system products. The third pattern, $4AFC, is reserved for customer use (as the
take illegal instruction trap (ILLEGAL) instruction).
Word patterns with bits 15–12 equaling 1010 or 1111 are distinguished as unimplemented
instructions, and separate exception vectors are assigned to these patterns to permit effi-
cient emulation. These separate vectors allow the operating system to emulate unimple-
mented instructions in software.
Exception processing for illegal instructions is similar to that for traps. After the instruction is
fetched and decoding is attempted, the processor determines that execution of an illegal
instruction is being attempted and starts exception processing. The exception stack frame
is then pushed on the supervisor stack, and the illegal instruction vector is fetched.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68307PU16 | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| MC68307PU16V | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| MC68307FG16 | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| MC68322FT16 | 16-BIT, 16.667 MHz, RISC PROCESSOR, PQFP160 |
| MC68331CFC20B1 | 32-BIT, 20 MHz, MICROCONTROLLER, PQFP132 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68307UM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor |
| MC68307V | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor |
| MC68322 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Printer Processor |
| MC68322AD | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Printer Processor |
| MC68322FT20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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