Table of Contents
MOTOROLA
MC68307 USER’S MANUAL
ix
3.2.2
Receiving the Bus Grant ........................................................................... 3-18
3.2.3
Acknowledgment of Mastership (Three-Wire Bus Arbitration Only) ......... 3-18
3.3
Bus Arbitration Control................................................................................ 3-19
3.4
Bus Error And Halt Operation ..................................................................... 3-27
3.4.1
Bus Error Operation .................................................................................. 3-27
3.4.2
Retrying the Bus Cycle ............................................................................. 3-29
3.4.3
Halt Operation........................................................................................... 3-30
3.4.4
Double Bus Fault ...................................................................................... 3-31
3.5
Reset Operation.......................................................................................... 3-31
3.6
Asynchronous Operation ............................................................................ 3-32
3.7
Synchronous Operation .............................................................................. 3-35
Section 4
EC000 Core Processor
4.1
Features........................................................................................................ 4-1
4.2
Processing States ......................................................................................... 4-1
4.3
Programming Model...................................................................................... 4-2
4.3.1
Data Format Summary ............................................................................... 4-3
4.3.2
Addressing Capabilities Summary .............................................................. 4-3
4.3.3
Notation Conventions ................................................................................. 4-4
4.4
EC000 Core Instruction Set Overview .......................................................... 4-6
4.5
Exception Processing ................................................................................... 4-9
4.5.1
Exception Vectors ..................................................................................... 4-12
4.6
Processing of Specific Exceptions .............................................................. 4-12
4.6.1
Reset Exception........................................................................................ 4-14
4.6.2
Interrupt Exceptions .................................................................................. 4-14
4.6.3
Uninitialized Interrupt Exception ............................................................... 4-15
4.6.4
Spurious Interrupt Exception .................................................................... 4-15
4.6.5
Instruction Traps ....................................................................................... 4-16
4.6.6
Illegal and Unimplemented Instructions .................................................... 4-16
4.6.7
Privilege Violations ................................................................................... 4-17
4.6.8
Tracing ...................................................................................................... 4-17
4.6.9
Bus Error................................................................................................... 4-18
4.6.10
Address Error............................................................................................ 4-18
4.6.11
Multiple Exceptions ................................................................................... 4-19
Section 5
System Integration Module
5.1
Module Operation ......................................................................................... 5-2
5.1.1
MC68307 System Configuration ................................................................. 5-2
5.1.1.1
Module Base Address Register Operation ............................................... 5-2
5.1.1.2
System Control Register Functions .......................................................... 5-4
5.1.1.3
System Protection Functions .................................................................... 5-5
5.1.2
Chip Select and Wait-State Logic ............................................................... 5-5
5.1.2.1
Programmable Data-Bus Size .................................................................. 5-6