EC000 Core Processor
MOTOROLA
MC68307 USER’S MANUAL
4-17
4.6.7 Privilege Violations
To provide system security, various instructions are privileged. An attempt to execute one
of the privileged instructions while in the user mode causes an exception. The privileged in-
structions are as follows:
AND Immediate to SR
MOVE USP
EOR Immediate to SR
OR Immediate to SR
MOVE to SR
RESET
MOVE from SR
RTE
MOVEC
STOP
MOVES
Exception processing for privilege violations is nearly identical to that for illegal instructions.
After the instruction is fetched and decoded and the processor determines that a privilege
violation is being attempted, the processor starts exception processing. The status register
is copied; the supervisor mode is entered; and tracing is turned off. The vector number is
generated to reference the privilege violation vector, and the current program counter and
the copy of the status register are saved on the supervisor stack. The saved value of the
program counter is the address of the first word of the instruction causing the privilege vio-
lation. Finally, instruction execution commences at the address in the privilege violation
exception vector.
4.6.8 Tracing
To aid in program development, the EC000 core includes a facility to allow tracing following
each instruction. When tracing is enabled, an exception is forced after each instruction is
executed. Thus, a debugging program can monitor the execution of the program under test.
The trace facility is controlled by the T-bit in the supervisor portion of the status register. If
the T-bit is cleared (off), tracing is disabled and instruction execution proceeds from instruc-
tion to instruction as normal. If the T-bit is set (on) at the beginning of the execution of an
instruction, a trace exception is generated after the instruction is completed. If the instruction
is not executed because an interrupt is taken or because the instruction is illegal or privi-
leged, the trace exception does not occur. The trace exception also does not occur if the
instruction is aborted by a reset, bus error, or address error exception. If the instruction is
executed and an interrupt is pending on completion, the trace exception is processed before
the interrupt exception. During the execution of the instruction, if an exception is forced by
that instruction, the exception processing for the instruction exception occurs before that of
the trace exception.
As an extreme illustration of these rules, consider the arrival of an interrupt during the exe-
cution of a TRAP instruction while tracing is enabled. First, the trap exception is processed,
then the trace exception, and finally the interrupt exception. Instruction execution resumes
in the interrupt handler routine.
After the execution of the instruction is complete and before the start of the next instruction,
exception processing for a trace begins. A copy is made of the status register. The transition
to supervisor mode is made, and the T-bit of the status register is turned off, disabling further
tracing. The vector number is generated to reference the trace exception vector, and the cur-