Table of Contents
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MC68307 USER’S MANUAL
MOTOROLA
5.1.2.2
Peripheral Chip Selects ............................................................................ 5-7
5.1.2.3
8051-Compatible Bus Chip Select ........................................................... 5-8
5.1.2.4
Global Chip Select Operation (Reset Defaults) ........................................ 5-8
5.1.2.5
Overlap in Chip Select Ranges ................................................................ 5-8
5.1.3
External Bus Interface Logic....................................................................... 5-9
5.1.3.1
M68000 Bus Interface .............................................................................. 5-9
5.1.3.2
8051-Compatible Bus Interface .............................................................. 5-10
5.1.3.3
Port A, Port B General-Purpose I/O Ports .............................................. 5-10
5.1.4
Interrupt Processing ................................................................................. 5-13
5.1.4.1
Interrupt Controller Logic ........................................................................ 5-14
5.1.4.2
Interrupt Vector Generation .................................................................... 5-15
5.1.4.3
IRQ7 Non-Maskable Interrupt ................................................................ 5-17
5.1.4.4
General-Purpose Interrupt Inputs ........................................................... 5-17
5.1.4.5
Peripheral Interrupt Handling ................................................................. 5-18
5.1.5
Low-Power Sleep Logic ............................................................................ 5-19
5.2
Programming Model ................................................................................... 5-20
5.2.1
System Configuration and Protection Registers ....................................... 5-22
5.2.1.1
Module Base Address Register (MBAR) ................................................ 5-22
5.2.1.2
System Control Register (SCR).............................................................. 5-23
5.2.1.3
System Status Register Bits Description ................................................ 5-23
5.2.1.4
System Control Register Bits Description. ............................................. 5-25
5.2.2
Chip Select Registers ............................................................................... 5-30
5.2.2.1
Base Registers (BR3–BR0).................................................................... 5-30
5.2.2.2
Option Registers (OR3–OR0) ................................................................ 5-32
5.2.3
External Bus Interface Control Registers ................................................. 5-34
5.2.3.1
Port A Control Register (PACNT) ........................................................... 5-34
5.2.3.2
Port A Data Direction Register (PADDR) ............................................... 5-35
5.2.3.3
Port A Data Register (PADAT) ............................................................... 5-35
5.2.3.4
Port B Control Register (PBCNT) ........................................................... 5-36
5.2.3.5
Port B Data Direction Register (PBDDR) ............................................... 5-36
5.2.3.6
Port B Data Register (PBDAT) ............................................................... 5-37
5.2.4
Interrupt Control Registers ....................................................................... 5-38
5.2.4.1
Latched Interrupt Control Registers 1,2 (LICR1,LICR2)......................... 5-38
5.2.4.2
Peripheral Interrupt Control Register (PICR).......................................... 5-39
5.2.4.3
Programmable Interrupt Vector Register (PIVR) .................................... 5-40
5.3
MC68307 Initialization Procedure............................................................... 5-41
5.3.1
Startup—Cold Reset................................................................................. 5-41
5.3.2
SIM Configuration ..................................................................................... 5-41
Section 6
Dual Timer Module
6.1
Overview....................................................................................................... 6-1
6.2
Module Operation ......................................................................................... 6-1
6.2.1
General-Purpose Timer Units ..................................................................... 6-1
6.2.2
Software Watchdog Timer .......................................................................... 6-3