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參數(shù)資料
| 型號： | MC68307CFG16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 16/264頁 |
| 文件大?。?/td> | 949K |
| 代理商： | MC68307CFG16 |
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System Integration Module
MOTOROLA
MC68307 USER’S MANUAL
5-17
5.1.4.3 IRQ7 NON-MASKABLE INTERRUPT. The IRQ7 input functions as a nonmaskable
interrupt (NMI) which always generates a level 7 interrupt to the EC000 core processor.
Priority level 7 cannot be disabled by the interrupt priority mask in the SR of the EC000 core
processor.
The interrupt controller logic passes an interrupt from the IRQ7 signal to the processor.
When the processor responds with an interrupt acknowledge cycle for level 7, the interrupt
controller issues the appropriate vector.
The IRQ7 input is edge sensitive and subject to two clock falling edges of synchronization
before being considered valid. If it is still asserted when a level 7 interrupt handler routine
exits (thus bringing the processor priority level below 7) then it is ignored until it negates for
one clock period before the next valid assertion. If the software needs to read the state of
the IRQ7 signal then the signal can be connected to an unused general-purpose input/
output pin, configured as an input.
An interlock is provided which prevents any interrupt including IRQ7 from reaching the
EC000 core processor until the PIVR is first written with a vector range. This allows the user
to ensure safety upon system startup before essential resources (e.g., chip selects for RAM
which contain stack) have been set up.
5.1.4.4 GENERAL-PURPOSE INTERRUPT INPUTS. The eight general-purpose latched
interrupt lines, INT1–INT8 share device pins with the high byte of port B I/O. To enable any
or all of these lines as dedicated interrupt inputs, the corresponding bit or bits in the PBCNT
must be set to one. As discussed already, the current state of the interrupt pin is always
available to software by reading the PBDAT, so that an interrupt handler can quickly
determine the source of the interrupt (it can also determine this by the vector number).
Before interrupts are enabled in system initialization software, the required IPL should be
programmed into the latched interrupt control registers (LICR1 and LICR2). Each of these
16-bit registers contains the priority setting bits (IPL) for four of the general-purpose interrupt
lines, along with pending interrupt reset (PIR) bits for each of them, allowing the interrupt
response software to clear any pending latched interrupt conditions. Note that the PIR bits
do not clear the source of interrupt; this must either happen automatically (by the interrupting
device hardware) after the interrupt condition is presented to the MC68307, or software must
explicitly address the device in question, and clear the condition manually. Note also that
when the IPL is changed for these latched interrupts, the PIR bit must also be set. This
avoids the possibility of any spurious interrupts occurring. Refer to Section 5.2.4 Interrupt
Control Registers for further details and programming information.
If the IPL for any one general-purpose interrupt line is programmed as 000, then that line is
effectively disabled. Another way to mask a particular interrupt line from causing interrupts,
without having to reprogram its priority level in the LICRx, is to clear the relevant bit in the
PBCNT.
When the EC000 runs an interrupt acknowledge cycle in response to the external interrupt
condition at a certain IPL, the interrupt controller module provides the appropriate vector as
discussed in Section 5.1.4.2 Interrupt Vector Generation. User software at the address
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