M-Bus Interface Module
MOTOROLA
MC68307 USER’S MANUAL
7-13
ENMASR
BCLR.B
#5,MBCR
; LAST ONE, GENERATE 'STOP'
; SIGNAL
NXMAR
MOVE.B
MBDR,RXBUF
; READ DATA AND STORE
RTE
7.4.5 Generation of Repeated START
At the end of data transfer, if the master still wants to communicate on the bus, it can gen-
erate another START signal followed by another slave address without first generate a
STOP signal. A program example is as shown.
RESTART
BSET.B
#2,MBCR
; ANOTHER START (RESTART)
MOVE.B
CALLING,MBDR
; TRANSMIT THE CALLING
; ADDRESS, D0=R/W-
7.4.6 Slave Mode
In slave interrupt service routine, the master addressed as slave bit (MAAS) should be
tested to check if a calling of its own address has just been received (refer to
Figure 7-4). If
MAAS is set, software should set the transmit/receive mode select bit (MTX bit of MBCR)
according to the R/W command bit (SRW). Writing to the MBCR clears the MAAS automat-
ically. Note that the only time MAAS is read as set is from the interrupt at the end of the
address cycle where an address match occurred; interrupts resulting from subsequent data
transfers clear MAAS. A data transfer may now be initiated by writing information to MBDR,
for slave transmits, or dummy reading from MBDR, in slave receive mode. The slave drives
SCL low between byte transfers, SCL is released when the MBDR is accessed in the
required mode.
In slave transmitter routine, RXAK must be tested before transmitting next byte of data.
When RXAK is set, this signals 'end of data' from the master receiver, which must then
switch from transmitter mode to receiver mode by software. This is followed by a dummy
read, which releases the SCL line so that the master can generate a STOP signal.
7.4.7 Arbitration Lost
Only one master can engage the bus at any one time. Those devices wishing to engage the
bus, but having lost arbitration, switch immediately to slave receive mode by hardware. Their
data output to the SDA line is stopped, but the SCL is still generated until the end of the byte
during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of
this transfer with MAL=1 and MSTA=0. If one master attempts to start transmission while
the bus is being engaged by another master, the hardware inhibits the transmission; the
MSTA bit is cleared without generating a STOP condition; an interrupt to CPU is generated
and MAL is set to indicate that the attempt to engage the bus failed. In these cases, the slave
service routine should test MAL first; MAL should be cleared by software if it is set.