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參數資料
| 型號： | MC68307CFG16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 80/264頁 |
| 文件大小： | 949K |
| 代理商： | MC68307CFG16 |
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Serial Module
8-10
MC68307 USER’S MANUAL
MOTOROLA
the error is not recognized until the final check is performed, and no indication exists as to
which character in the message is at fault.
In either mode, reading the USR does not affect the FIFO. The FIFO is 'popped' only when
the receive buffer is read. The USR should be read prior to reading the receive buffer. If all
three of the FIFO's receiver holding registers are full when a new character is received, the
new character is held in the receiver shift register until a FIFO position is available. If an addi-
tional character is received during this state, the contents of the FIFO are not affected. How-
ever, the character previously in the receiver shift register is lost, and the OE bit in the USR
is set when the receiver detects the start bit of the new overrunning character.
To support control flow capability, the receiver can be programmed to automatically negate
and assert RTS. When in this mode, RTS is automatically negated by the receiver when a
valid start bit is detected and the FIFO stack is full. When a FIFO position becomes avail-
able, RTS is asserted by the receiver. Using this mode of operation, overrun errors are pre-
vented by connecting the RTS to the CTS input of the transmitting device.
Note that in order to use the RTS or CTS signals, the MC68307 port B control register must
be set up to enable the corresponding I/O pins for these functions. By default these signals
function as port B bits 4 and 5 respectively.
If the FIFO stack contains characters and the receiver is disabled, the characters in the FIFO
can still be read by the CPU. If the receiver is reset, the FIFO stack and all receiver status
bits, corresponding output ports, and interrupt request are reset. No additional characters
are received until the receiver is re-enabled.
8.3.3 Looping Modes
The UART can be configured to operate in various looping modes as shown in Figure 8-7.
These modes are useful for local and remote system diagnostic functions. The modes are
described in the following paragraphs with further information available in Section 8.4 Reg-
The UART's transmitter and receiver should both be disabled when switching between
modes. The selected mode is activated immediately upon mode selection, regardless of
whether a character is being received or transmitted.
8.3.3.1 AUTOMATIC ECHO MODE. In this mode, the UART automatically retransmits the
received data on a bit-by-bit basis. The local CPU-to-receiver communication continues nor-
mally, but the CPU-to-transmitter link is disabled. While in this mode, received data is
clocked on the receiver clock and retransmitted on TxD. The receiver must be enabled, but
the transmitter need not be enabled.
Since the transmitter is not active, the TxEMP and TxRDY bits in USR are inactive, and data
is transmitted as it is received. Received parity is checked, but not recalculated for transmis-
sion. Character framing is also checked, but stop bits are transmitted as received. A
received break is echoed as received until the next valid start bit is detected.
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相關代理商/技術參數 |
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| MC68307UM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor |
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