Signal Description
2-6
MC68307 USER’S MANUAL
MOTOROLA
Address line A0 is included for 8-bit data-bus interfaces only, i.e., the 8051-compatible bus,
as described above, and also the dynamically-sized 68000 bus when programmed to use
an 8-bit data-bus width. During 16-bit data-bus width cycles, the A0 output is meaningless,
and should be ignored, as it may well hold a misleading value. The UDS and LDS signals
should be used to further decode the even/odd byte access in this case.
2.1.2 Data Bus (D15–D0)
This 16-bit bidirectional parallel bus contains the data being transferred to or from the
MC68307 during M68000 bus cycles. Its value should be ignored during 8051-compatible
bus read and write cycles, it is not three-stated in either case. A read or write operation may
transfer 8 or 16 bits of data (one or two bytes) in one bus cycle.
During an internal peripheral access, the data bus reflects the value read or written, for emu-
lation and debug purposes. Care is required, therefore, if external buffers are needed.
The data bus has a programmable 8-bit bus size option for M68000 bus cycles, which is
used in conjunction with the programmable chip-select dynamic bus sizing. If a chip select
is configured for 8-bit port size, any 16-bit transfers appears externally as two 8-bit transfers.
In this case, the 8-bit data uses the D15–D8 lines only.
2.2 CHIP SELECTS
The programmable chip select outputs allow system designers to interface the MC68307
directly to memory and peripheral devices without having to perform address decode requir-
ing additional external logic. Although they can be programmed for many different configu-
rations, each one has a particular usage to which it is tailored, giving added functionality.
They are asserted coincident with the address strobe (AS) output, and are all active-low.
Refer to Section 5 System Integration Module for details of how the chip selects can be
programmed.
2.2.1 Chip Select 0 (CS0)
This signal is the chip select for a boot ROM containing the reset vectors and initialization
program. From a cold reset, this chip select is asserted on every bus cycle in the first 8K
bytes of address space until is is programmed otherwise. The BUSW0 pin specifies how this
chip select behaves from cold reset, whether it is an 8-bit wide data bus access (BUSW0=0)
or a 16-bit wide data bus access (BUSW0=1).
2.2.2 Chip Select 1 (CS1)
This signal is primarily intended to be an enable for a RAM memory device. From a cold
reset, this signal does not assert until it is programmed with a valid base address and
address mask. The data bus width for memory devices selected by this chip select is also
programmable, between 8- and 16-bit data, in the system control register.
2.2.3 Chip Select 2 (CS2, CS2B, CS2C, CS2D)
Although the CS2/CS2A pin can be used as a general-purpose M68000 chip-select (CS2),
it can, together with the CS2B, CS2C, CS2D signals, be used to enable one of four miscel-
laneous peripherals. The CS2 output address range can be relocated like any of the other