
System Integration Module
5-34
MC68307 USER’S MANUAL
MOTOROLA
CFC—Compare Function Code
0 = The function code 2-0 bits (FC2–FC0) in the base register (BR) are ignored. The
chip select is asserted without comparing the FCx bits.
1 = The FCx bits on the BR are compared. The address space compare logic uses the
FCx bits to assert the CSx line.
After system reset, this bit defaults to one.
NOTE
Even when CFC=0, if the function code lines are internally gen-
erated as “111” (CPU space cycle), the chip select is not assert-
ed.
5.2.3 External Bus Interface Control Registers
These consist only of the control and data registers associated with the external general-
purpose/dedicated I/O signals. All other configuration of the external bus interface is
contained within either the system configuration or the chip select logic blocks.
5.2.3.1 PORT A CONTROL REGISTER (PACNT). This 8-bit read/write register is used by
the user to specify the function of the I/O lines in port A, the 8-bit I/O port, as general-purpose
I/O, or dedicated I/O for the on-chip peripherals.
From a cold reset, these register bits are all cleared, thus configuring all port A I/O lines as
general-purpose inputs. Bootstrap software must write an appropriate value into PACNT to
reflect the system hardware setup, before any of the peripherals which need port A pins can
be used properly. Pullup resistors may be required if the dedicated peripheral outputs (which
share port A pins) are used, as these signals would otherwise momentarily float at cold reset
until configured in the PACNT register.
CA7–CA0—Port A Pin Assignment Control
These bits are used to determine whether the corresponding port A input/output line are
configured as general-purpose functions or dedicated functions.
0 = The corresponding port A I/O bit is to be a
general-purpose I/O bit.
1 = The corresponding port A I/O bit is to be a
dedicated I/O bit.
PACNT
MBASE+$011
7
0
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
RESET:
0
Read/Write
Supervisor or User