Introduction
1-4
MC68307 USER’S MANUAL
MOTOROLA
and a peripheral might not be compatible nor run from the same clock, requiring time delays
or other special design considerations.
In an M68300 family component, the major functions and glue logic are all properly con-
nected internally, timed with the same clock, fully tested, and uniformly documented. Only
essential signals are brought out to pins. The primary package is the surface-mount plastic
QFP for the smallest possible footprint.
1.2 MC68307 ARCHITECTURE
To improve total system throughput and reduce part count, board size and cost of system
implementation, the MC68307 integrates a powerful processor, intelligent peripheral mod-
ules, and typical system interface logic. These functions include the SIM07, timers, UART,
M-bus interface, and 8051-compatible bus interface.
The EC000 core processor communicates with these modules via an internal bus, providing
the opportunity for fully synchronized communication between all modules and allowing
interrupts to be handled in parallel with data transfers, greatly improving system perfor-
mance.
1.2.1 EC000 Core Processor
The EC000 is a core implementation of the M68000 32-bit microprocessor architecture. The
programmer can use any of the eight 32-bit data registers for fast manipulation of data and
any of the eight 32-bit address registers for indexing data in memory. Flexible instructions
support data movement, arithmetic functions, logical operations, shifts and rotates, bit set
and clear, conditional and unconditional program branches, and overall system control.
The EC000 core can operate on data types of single bits, binary-coded decimal (BCD) digits,
and 8, 16, and 32 bits. The integrated chip selects allow peripherals and data in memory to
reside anywhere in the 16-Mbyte linear address space. A supervisor operating mode pro-
tects system-level resources from the more restricted user mode, allowing a true virtual envi-
ronment to be developed. Many addressing modes complement these instructions,
including predecrement and postincrement, which allow simple stack and queue mainte-
nance and scaled indexing for efficient table accesses. Data types and addressing modes
are supported orthogonally by all data operations and with all appropriate addressing
modes. Position-independent code is easily written.
Like all M68000 family processors, the EC000 core recognizes interrupts of seven different
priority levels and, in conjunction with the integrated interrupt controller, allows a pro-
grammed vector to direct the processor to the desired service routine. Internal trap excep-
tions ensure proper instruction execution with good addresses and data, allow operating
system intervention in special situations, and permit instruction tracing. The hardware time-
out can terminate bad memory accesses before instructions process data incorrectly. The
EC000 core provides 2.7 millions of bits per second (MIPS) at 16.67 MHz.
1.2.2 System Integration Module (SIM07)
The SIM07 provides the external bus interface for the EC000 core. It also eliminates much
of the glue logic that typically supports a microprocessor and its interface with the peripheral