System Integration Module
5-28
MC68307 USER’S MANUAL
MOTOROLA
UACW—UART Clock Wakeup
Setting this bit allows a transition on the RxD pin of the UART to cause an automatic re-
start of the UART clock, allowing it to receive a character, even when the UART had its
clock stopped by the setting of the UACD bit. If the UART is configured to cause an inter-
rupt on Rx character or framing error, and the UART interrupt is enabled in the peripheral
interrupt control register, then the reception of a character causes an interrupt and a
wakeup of the EC000 core processor if it was in low-power mode (as enabled by the
LPEN bit).
0 = A transition on RxD does not restart the UART clock if disabled by UACD.
1 = A transition on RxD restarts the UART clock if disabled by UACD.
After a cold reset, this bit is cleared.
Note that software should also handle framing errors if this feature is used, in order to
avoid spurious transitions on RxD causing unnecessary power consumption. If interrupt
on framing error is not enabled in this situation, then the UART module remains active
even if the EC000 core is in low-power mode. The interrupt handler would normally set
the UART and EC000 core back into low-power mode.
UACD—UART Clock Disable
Setting this bit disables the clock to the UART module immediately. As such it should only
be done when no essential data is being transmitted or received by the UART channel.
0 = The clock to the UART module is active.
1 = The clock to the UART module is disabled.
After a cold reset, this bit is cleared, and so the UART clock is active.
Refer also to the description of the UART clock wakeup (UACW bit above).
TMCD—Timer Clock Disable
Setting this bit disables the clock to the timer module immediately. As such it should only
be done when no software task depends on a timer channel timeout for completion, de-
pending on the user's application.
0 = The clock to the timer module is active.
1 = The clock to the timer module is disabled.
After a cold reset, this bit is cleared, and so the timer clock is active.
MBCD—M-Bus Clock Disable
Setting this bit disables the clock to the M-bus module immediately. As such it should only
be done when no essential data is being transmitted or received by the M-bus channel.
0 = The clock to the M-bus module is active.
1 = The clock to the M-bus module is disabled.
After a cold reset, this bit is cleared, and so the M-bus clock is active.
LPEN—Low-Power Sleep Mode Enable
Setting this bit allows the EC000 core processor to be placed into the low-power sleep
mode, stopping its clock input and holding the processor in a known state ready for wake-
up as described previously. The sequence for user software to stop the EC000 core clock