Bus Operation
3-37
MC68307 USER’S MANUAL
MOTOROLA
processor. If DTACK is asserted before the falling edge of S4 and satisfies the
input setup time defined by parameter #47, the processor enters S5 and the
bus cycle continues. If DTACK is asserted but without meeting the setup time
defined by parameter #47, the processor may recognize the signal and
continue the bus cycle; the result is unpredictable. If DTACK is not asserted
before the next rise of clock, the bus cycle remains in S4, and wait states
(complete clock cycles) are inserted until one of the bus cycle terminations is
met. DTACK is normally generated by the internal wait-state generator.
STATE 5
S5 is a low period of the clock, during which the processor does not alter any
signal.
STATE 6
S6 is a high period of the clock, during which data for a read operation is set
up relative to the falling edge (entering S7). Parameter #27 defines the
minimum period by which the data must precede the falling edge. For a write
operation, the processor changes no signal during S6.
STATE 7
On the falling edge of the clock entering S7, the processor latches data and
negates AS and UDS/LDS during a read cycle. The hold time for these
strobes from this falling edge is specified by parameter #12. The hold time for
data relative to the negation of AS and UDS/LDS is specified by parameter
#29. For a write cycle, only AS and UDS/LDS, are negated; timing parameter
#12 also applies.
On the rising edge of the clock, at the end of S7 (which may be the start of S0
for the next bus cycle), the processor places the address bus in the high-
impedance state. During a write cycle, the processor also places the data bus
in the high-impedance state and drives R/W high. External logic circuitry
should respond to the negation of the AS and UDS/LDS by negating DTACK,
if it was asserted externally. Parameter #28 is the hold time for DTACK.
Figure 3-34 shows a synchronous read cycle and the important timing parameters that
apply. The timing for a synchronous read cycle, including relevant timing parameters, is
A key consideration when designing in a synchronous environment is the timing for the
assertion of DTACK by an external device. To properly use external inputs, the processor
must synchronize these signals to the internal clock. The processor must sample the exter-
nal signal, which has no defined phase relationship to the CPU clock, which may be chang-
ing at sampling time, and must determine whether to consider the signal high or low during
the succeeding clock period. Successful synchronization requires that the internal machine
receives a valid logic level, whether the input is high, low, or in transition.
Parameter #47 of Section 11.7 AC Electrical Specifications—Read and Write Cycles
(VCC = 5.0V
± 0.5V or 3.3Vdc ± 0.3V; GND = 0Vdc; TA = TL to TH) (see Figure 11-3 and
Figure 11-4) is the asynchronous input setup time. Signals that meet parameter #47 are
guaranteed to be recognized at the next falling edge of the system clock. However, signals
that do not meet parameter #47 are not guaranteed to be recognized. In addition, if DTACK