MOTOROLA
MC68307 USER’S MANUAL
10-1
SECTION 10
APPLICATIONS INFORMATION
10.1 MC68307 MINIMUM STAND-ALONE SYSTEM HARDWARE
This section details a simple stand-alone system using the MC68307. It demonstrates the
simplicity of system hardware design and inherent low system chip count when using the
highly integrated MC68307. The system hardware is shown in
Figure 10-1.The 5-V design consists of a 16.67MHz MC68307, 8-bit boot EPROM, 16-bit SRAM, an
RS232 driver and a few logic gates. It is considered stand-alone in that a dumb terminal (or
terminal emulator) can be serially connected to the UART (via RS232) and used to control
the system.
10.1.1 MC68307 Signal Configuration
BUSW0 is tied low, meaning that the MC68307 boots up in 8-bit mode after reset. Alterna-
tively, BUSW0 could use a pull-up resistor to select 16-bit mode at reset, requiring a further
8-bit or a more expensive 16-bit EPROM.
Clock crystal connection is simple.
Figure 10-1 shows a typical configuration. The usual
oscillator start-up capacitors and bias resistor are included on-chip. The crystal parameters
do not need to be particular values; Co (Shunt capacitance) < 10pF and Rx = 50 ohms were
used in this case. An oscillator module could be used if preferred, connected to the EXTAL
pin with XTAL unconnected.
CLKOUT is typically used as the reference clock for external system peripherals. In this case
it remains unconnected.
The RSTIN input can be used to extend the power-on reset time if desired. If slower system
peripherals require an extended RESET at power-up, an RC network attached to RSTIN can
be used. In this case, the standard 32K clock stretch time at power-on suffices. At
16.67MHz, the 32K clocks equate to a 2ms RESET hold-on interval allowing the clock and
power supply to normalize. RSTIN is attached to a debounced button to cold reset the
MC68307 (and the system if other devices are connected to the RESET output). On each
reset button press, the device is held in reset for the same 32K clocks as power-on.
RESET and HALT are bidirectional open drain lines, requiring low value pull-up resistors to
maintain the inactive state when not asserted. RESET and HALT are not used here, but
could be asserted together to reset the system hardware if required. In this case the reset
is not lengthened internally by 32k clocks.
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