參數(shù)資料
型號(hào): MC68307CFG16
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 6/264頁(yè)
文件大?。?/td> 949K
代理商: MC68307CFG16
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)
System Integration Module
5-8
MC68307 USER’S MANUAL
MOTOROLA
5.1.2.3 8051-COMPATIBLE BUS CHIP SELECT. Chip select 3 (CS3 signal) can be used
to define the addressing range of the 8051-compatible bus mode, when this mode is
enabled in the SCR E8051 bit. Otherwise (if the 8051-compatible bus mode is not used) chip
select 3 is available for any general purpose memory or peripheral. In this case, the 8051-
compatible bus read and write strobes (RD and WR), and the address latch enable (ALE)
signal are always negated. This bus always uses an 8-bit data-bus width, and so the
BUSW3 bit in the SCR should be set along with the E8051 bit.
5.1.2.4 GLOBAL CHIP SELECT OPERATION (RESET DEFAULTS). Chip
select
0
is
initialized from cold reset to assert in response to any address in the first 8K bytes of memory
space, in order to ensure a chip select to the boot ROM or EPROM, to fetch the reset vector
and execute the initialization code, which should set up the module base address and the
four chip select ranges early on in that initialization sequence.
The data bus port size for CS0 on reset, and hence the data width of the boot ROM device,
are programmed by placing logic 0 or 1 on the BUSW pin during reset, for 8-bit and 16-bit
wide data bus respectively.
The other 3 chip selects are initialized to be invalid, and so do not assert until they are
programmed.
5.1.2.5 OVERLAP IN CHIP SELECT RANGES. The user should not normally program
more than one chip select line to the same area. If this accidentally occurs, only one chip
select line is driven because of internal line priorities. CS0 has the highest priority, and CS3
the lowest. The address compare logic sets the address decode conflict (ADC) status bit in
the SCR, and also generates a bus error (or BERR is asserted) if the address decode
conflict enable (ADCE) bit was set by the user in the SCR.
BERR is never asserted on write accesses to the chip select registers.
If one chip select is programmed to be read-only, and another is programmed to be write-
only, then there is no overlap conflict between these two chip selects, and the address
decode conflict (ADC) status bit in the SCR is not set.
When the CPU attempts to write to a read-only location, as programmed by the user when
setting up the chip selects, the chip select logic sets the write protect violation (WPV) bit in
the SCR, and will also generate BERR if the write protect violation enable (WPVE) bit is set
in the SCR. The CSx line is not asserted.
NOTE
The chip select logic is reset only on cold reset (assertion of
RESET and HALT, or RSTIN). The chip select (CSx) lines are
never asserted on accesses to the MBAR and SCR locations.
Thus, it is very convenient to use CSx lines to select external
ROM/RAM that overlaps or encloses the MBAR and SCR
相關(guān)PDF資料
PDF描述
MC68307PU16 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100
MC68307PU16V 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100
MC68307FG16 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100
MC68322FT16 16-BIT, 16.667 MHz, RISC PROCESSOR, PQFP160
MC68331CFC20B1 32-BIT, 20 MHz, MICROCONTROLLER, PQFP132
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68307UM 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor
MC68307V 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor
MC68322 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Printer Processor
MC68322AD 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Printer Processor
MC68322FT20 制造商:Rochester Electronics LLC 功能描述:- Bulk