System Integration Module
MOTOROLA
MC68307 USER’S MANUAL
5-13
5.1.4 Interrupt Processing
Interrupt processing on the MC68307 involves four steps. A typical sequence is as follows:
1. The interrupt controller on the MC68307 collects interrupt events from on and off-chip
peripherals, prioritizes them, and presents the highest priority request to the EC000
core processor.
2. The EC000 core processor responds to the interrupt request by executing an interrupt
acknowledge bus cycle after the completion of the current instruction.
3. The interrupt controller recognizes the interrupt acknowledge cycle and places the in-
terrupt vector for that interrupt request onto the EC000 core processor bus.
4. The EC000 core processor reads the vector, reads the address of the interrupt handler
in the exception vector table, and then begins execution at that address.
Steps 2 and 4 are the responsibility of the EC000 core processor on the MC68307, whereas
steps 1 and 3 are the responsibility of the interrupt controller on the MC68307.
External devices are forbidden from responding to IACK cycles with a vector, this is always
done by the interrupt controller. No FC2–FC0 signals are available for decode.
The EC000 core processor is not modified for use on the MC68307, thus steps 2 and 4
operate exactly as they would on the M68000 devices. In step 2, the EC000 processor
status register (SR) is available to mask interrupts globally or to determine which priority
levels can currently generate interrupts. Also in step 2, the interrupt acknowledge cycle is
executed.
The interrupt acknowledge cycle carries out a M68000 bus read cycle except that FC2–FC0
are encoded as 111, A3–A1 are encoded with the interrupt priority level (1–7, with 7 (i.e.,
111) being the highest), and A19–A16 are driven high. This cycle is visible externally, but no
chip selects are asserted.
In step 4, the EC000 core processor reads the vector number, multiplies it by 4 to get the
vector address, fetches a 4-byte program address from that vector address, and then jumps
to that 4-byte address. That 4-byte address is the location of the first instruction in the
interrupt handler.
Steps 1 and 3 are the responsibility of the interrupt controller on the MC68307. Here a
number of configuration options are available. For instance, for step 1 (interrupt generation),
all interrupt sources have programmable interrupt priority levels (IPL). In step 3 (vector
response), a block of vectors can be allocated to the interrupt sources under program
control. These and other interrupt controller options are introduced in the following
paragraphs.