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Revision 1.1
G
Architecture Overview
(Continued)
1.1.6
The GX1 module integrates the following functions tradi-
tionally implemented using external devices:
Integrated Functions
SDRAM memory controller
PCI bridge
The module has also been enhanced to support VSA tech-
nology implementation.
1.1.6.1
The memory controller drives a 64-bit SDRAM port directly.
Up to two module banks of SDRAM are supported. Each
module bank can have two or four component banks
depending on the memory size and organization. The max-
imum configuration is two module banks with four compo-
nent banks, each providing a total of 16 open banks. The
maximum memory size is 512 MB.
Memory Subsystem
The memory controller handles multiple requests for mem-
ory data from the GX1 module, and other sources via Fast-
PCI. The memory controller contains extensive buffering
logic that helps minimize contention for memory band-
width. The memory controller cooperates with the internal
bus controller to determine the cacheability of all memory
references.
1.1.6.2
The GX1 module incorporates a full-function PCI interface
module that includes the PCI arbiter. All accesses to exter-
nal I/O devices are sent over the Fast-PCI bus, although
PCI Controller
most memory accesses are serviced by the SDRAM con-
troller. The internal bus interface unit contains address
mapping logic that determines if memory accesses are tar-
geted for the SDRAM or for the PCI bus. The PCI bus in an
SC1100- based system is 3.3 volt only. Do not connect 5
volt devices on this bus.
1.1.6.3
The GX1 module communicates with the Core Logic mod-
ule via a Fast-PCI bus that can work at up to 66 MHz. The
Fast-PCI bus is internal for the SC1100 and is connected
to the Configuration Block.
Fast-PCI Bus
1.1.7
Differences from Standalone GX1
1.1.7.1
The SC1100’s device ID is contained within the GX1 mod-
ule. Software can detect the revision by reading the DIR0
and DIR1 Configuration registers (see Configuration regis-
ters in the G
eode GX1 Processor Series datasheet
). The
SC1100 device errata contains the specific values.
Device ID
1.1.7.2
The GX1 module is connected to external SDRAM DIMMs.
For more information see Section 2.4.2 "Memory Interface
Signals" on page 37, and the “Memory Controller” chapter
in the
GX1 Processor Series datasheet
. The drive
strength/slew control in the memory controller block (see
Table 1-1) is different from the standalone GX1 processor.
SDRAM
Table 1-1. SC1100 GX1 Module System Memory Buffer Strength Control
Bit
Description
GX_BASE+Memory Offset 8400h
Width: DWORD
MC_MEM_CNTRL1 (R/W)
Reset Value: 248C0040h
31:30
28:27
25:24
MD[63:0] Drive Strength:
11 is strongest, 00 is weakest.
MA[12:0] and BA[1:0] Drive Strength:
11 is strongest, 00 is weakest.
RASA#, CASA#, WEA#, CS[1:0]#, CKEA, DQM[7:0] Drive Strength:
11 is strongest, 00 is weakest.
3
X-Bus Round Robin.
Must be written with 1.
GX_BASE+Memory Offset 8404h
Width: DWORD
MC_MEM_CNTRL2 (R/W)
Reset Value: 00000801h
13:12
SCLK High Drive/Slew Control:
Controls the high drive and slew rate of SDCLK[3:0] and SDCLK_OUT.
11 is strongest, 00 is weakest.