Revision 1.1
205
www.national.com
G
Core Logic Module
(Continued)
13:12
LPC Microsoft Sound System (MSS) Address Select.
Selects I/O Port:
00: 530h-537h
10: E80h-E87h
01: 604h-60Bh
11: F40h-F47h
Selected address range is enabled via F0BAR1+I/O Offset 10h[5].
LPC MIDI Address Select.
Selects I/O Port:
00: 300h-301h
10: 320h-321h
01: 310h-311h
11: 330h-331h
Selected address range is enabled via F0BAR1+I/O Offset 10h[4].
LPC Audio Address Select.
Selects I/O Port:
00: 220h-233h
10: 260h-273h
01: 240h-253h
11: 280h-293h
Selected address range is enabled via F0BAR1+I/O Offset 10h[3].
LPC Serial Port 1 Address Select.
Selects I/O Port:
000: 3F8h-3FFh
010: 220h-227h
001: 2F8h-2FFh
011: 228h-22Fh
Selected address range is enabled via F0BAR1+I/O Offset 10h[2].
LPC Serial Port 0 Address Select.
Selects I/O Port:
000: 3F8h-3FFh
010: 220h-227h
001: 2F8h-2FFh
011: 228h-22Fh
Selected address range is enabled via F0BAR1+I/O Offset 10h[1].
LPC Parallel Port Address Select.
Selects I/O Port:
00: 378h-37Fh (+778h-77Fh for ECP)
01: 278h-27Fh (+678h-67Fh for ECP) (Note)
10: 3BCh-3BFh (+7BCh-7BFh for ECP)
11: Reserved
Selected address range is enabled via F0BAR1+I/O Offset 10h[0].
Note:
279h is read only, writes are forwarded to ISA for PnP.
11:10
9:8
7:5
100: 238h-23Fh
101: 2E8h-2EFh
110: 338h-33Fh
111: 3E8h-3EFh
4:2
100: 238h-23Fh
101: 2E8h-2EFh
110: 338h-33Fh
111: 3E8h-3EFh
1:0
Offset 18h-1Bh
LAD_D1 — LPC Address Decode 1 Register (R/W)
Reset Value: 00000000h
31:16
15:9
Reserved.
Must be set to 0.
Wide Generic Base Address Select.
Defines a 512 byte space. Can be mapped anywhere in the 64 KB I/O space. AC97
and other configuration registers are expected to be mapped to this range. It is wide enough to allow many unforeseen
devices to be supported. Enabled at F0BAR1+I/O Offset 10h[9].
Note:
The selected range must not overlap any address range that is positively decoded by F0BAR1+I/O Offset 10h bits
[17], [14:10], and [8:0].
Reserved.
Must be set to 0.
8:0
Offset 1Ch-1Fh
LPC_ERR_SMI — LPC Error SMI Register (R/W)
Reset Value: 00000080h
31:10
9
Reserved.
Must be set to 0.
SMI Serial IRQ Enable.
Allows serial IRQ to generate an SMI.
0: Disable.
1: Enable.
Top Level SMI status is reported at F1BAR0+I/O Offset 02h[3].
Second level status is reported at bit 6 of this register.
SMI Configuration for LPC Error Enable.
Allows LPC errors to generate an SMI.
0: Disable.
1: Enable.
Top Level SMI status is reported at F1BAR0+I/O Offset 02h[3].
Second level status is reported at bit 5 of this register.
Reserved. (Read Only).
8
7
Table 5-31. F0BAR1+I/O Offset xxh: LPC Interface Configuration Registers (Continued)
Bit
Description