Revision 1.1
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G
Core Logic Module
(Continued)
16
ConnectStatusChange.
This bit indicates a connect or disconnect event has been detected. Writing a 1 clears this bit.
Writing a 0 has no effect.
0: No connect/disconnect event.
1: Hardware detection of connect/disconnect event.
If DeviceRemoveable is set, this bit resets to 1.
15:10
Reserved.
Read/Write 0s.
9
Read: LowSpeedDeviceAttached.
This bit defines the speed (and bud idle) of the attached device. It is only valid when
CurrentConnectStatus is set.
0: Full speed device.
1: Low speed device.
Write: ClearPortPower.
Writing a 1 clears PortPowerStatus. Writing a 0 has no effect.
8
Read: PortPowerStatus.
This bit reflects the power state of the port regardless of the power switching mode.
0: Port power is off.
1: Port power is on.
If NoPowerSwitching is set, this bit is always read as 1.
Write: SetPortPower.
Writing a 1 sets PortPowerStatus. Writing a 0 has no effect.
7:5
Reserved.
Read/Write 0s.
4
Read: PortResetStatus.
0: Port reset signal is not active.
1: Port reset signal is active.
Write: SetPortReset.
Writing a 1 sets PortResetStatus. Writing a 0 has no effect.
3
Read: PortOverCurrentIndicator.
This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only
valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set.
0: No over-current condition.
1: Over-current condition.
Write: ClearPortSuspend.
Writing a 1 initiates the selective resume sequence for the port. Writing a 0 has no effect.
2
Read: PortSuspendStatus.
0: Port is not suspended.
1: Port is selectively suspended.
Write: SetPortSuspend.
Writing a 1 sets PortSuspendStatus. Writing a 0 has no effect.
1
Read: PortEnableStatus.
0: Port disabled.
1: Port enabled.
Write: SetPortEnable.
Writing a 1 sets PortEnableStatus. Writing a 0 has no effect.
0
Read: CurrentConnectStatus.
0: No device connected.
1: Device connected.
If DeviceRemoveable is set (not removable) this bit is always 1.
Write: ClearPortEnable.
Writing 1 a clears PortEnableStatus. Writing a 0 has no effect.
Note:
This register is reset by the UsbReset state.
Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit
Description